Mar 09 09:28:02.525 VTTY: Console port: waiting connection on tcp port 2005 for protocol IPv4 (FD 12)
Mar 09 09:28:02.588 slot0: C/H/S settings = 0/4/32
Mar 09 09:28:02.588 slot1: C/H/S settings = 0/4/32
Mar 09 09:28:02.950 C3745_BOOT: starting instance (CPU0 PC=0xffffffffbfc00000,idle_pc=0x60aa5f14,JIT on)
Mar 09 09:28:02.950 CPU0: CPU_STATE: Starting CPU (old state=2)...
Mar 09 09:28:02.970 ROM: Microcode has started.
Mar 09 09:28:02.974 ROM: trying to read bootvar 'WARM_REBOOT'
Mar 09 09:28:02.976 CPU0: IO_FPGA: write to unknown addr 0x30, value=0x0, pc=0xffffffff80a9d228 (size=1)
Mar 09 09:28:02.976 CPU0: IO_FPGA: read from unknown addr 0x30, pc=0xffffffff80a9d23c (size=1)
Mar 09 09:28:03.127 CPU0: IO_FPGA: read from unknown addr 0x6, pc=0x6026eef8 (size=2)
Mar 09 09:28:03.129 CPU0: IO_FPGA: read from unknown addr 0x10000a, pc=0x60276800 (size=2)
Mar 09 09:28:03.129 CPU0: IO_FPGA: write to unknown addr 0x10000a, value=0x0, pc=0x60276810 (size=2)
Mar 09 09:28:03.129 ROM: unhandled syscall 0x00000047 at pc=0x60a9e9bc (a1=0x80007dac,a2=0x00000010,a3=0xbfb00000)
Mar 09 09:28:04.027 ROM: trying to read bootvar 'RANDOM_NUM'
Mar 09 09:28:04.072 CPU0: IO_FPGA: write to unknown addr 0x2e, value=0x20, pc=0x60283d28 (size=2)
Mar 09 09:28:04.073 CPU0: PCI: read request for device 'gt96100' at pc=0x60286c50: bus=0,device=0,function=0,reg=0x00
Mar 09 09:28:04.073 CPU0: PCI: read request for device 'gt96100' at pc=0x60286c54: bus=0,device=0,function=0,reg=0x00
Mar 09 09:28:04.073 CPU0: PCI: read request for device 'gt96100' at pc=0x60286a04: bus=0,device=0,function=0,reg=0x08
Mar 09 09:28:04.073 CPU0: PCI: write request (data=0x00000000) for device 'gt96100' at pc=0x60286b4c: bus=0,device=0,function=0,reg=0x10
Mar 09 09:28:04.073 CPU0: PCI: write request (data=0x00000000) for device 'gt96100' at pc=0x60286b50: bus=0,device=0,function=0,reg=0x10
Mar 09 09:28:04.073 CPU0: PCI: write request (data=0x00000000) for device 'gt96100' at pc=0x60286b4c: bus=0,device=0,function=0,reg=0x90
Mar 09 09:28:04.073 CPU0: PCI: write request (data=0x00000000) for device 'gt96100' at pc=0x60286b50: bus=0,device=0,function=0,reg=0x90
Mar 09 09:28:04.073 CPU0: PCI: write request (data=0x10000000) for device 'gt96100' at pc=0x60286b4c: bus=0,device=0,function=0,reg=0x14
Mar 09 09:28:04.073 CPU0: PCI: write request (data=0x10000000) for device 'gt96100' at pc=0x60286b50: bus=0,device=0,function=0,reg=0x14
Mar 09 09:28:04.073 CPU0: PCI: write request (data=0x10000000) for device 'gt96100' at pc=0x60286b4c: bus=0,device=0,function=0,reg=0x94
Mar 09 09:28:04.073 CPU0: PCI: write request (data=0x10000000) for device 'gt96100' at pc=0x60286b50: bus=0,device=0,function=0,reg=0x94
Mar 09 09:28:04.073 CPU0: PCI: write request (data=0x04000000) for device 'gt96100' at pc=0x60286b4c: bus=0,device=0,function=0,reg=0x20
Mar 09 09:28:04.073 CPU0: PCI: write request (data=0x04000000) for device 'gt96100' at pc=0x60286b50: bus=0,device=0,function=0,reg=0x20
Mar 09 09:28:04.073 CPU0: PCI: write request (data=0x04000000) for device 'gt96100' at pc=0x60286b4c: bus=0,device=0,function=0,reg=0xa0
Mar 09 09:28:04.073 CPU0: PCI: write request (data=0x04000000) for device 'gt96100' at pc=0x60286b50: bus=0,device=0,function=0,reg=0xa0
Mar 09 09:28:04.073 CPU0: PCI: write request (data=0x00000146) for device 'gt96100' at pc=0x60286b4c: bus=0,device=0,function=0,reg=0x04
Mar 09 09:28:04.073 CPU0: PCI: write request (data=0x00000146) for device 'gt96100' at pc=0x60286b50: bus=0,device=0,function=0,reg=0x04
Mar 09 09:28:04.073 CPU0: PCI: write request (data=0x00000146) for device 'gt96100' at pc=0x60286b4c: bus=0,device=0,function=0,reg=0x84
Mar 09 09:28:04.073 CPU0: PCI: write request (data=0x00000146) for device 'gt96100' at pc=0x60286b50: bus=0,device=0,function=0,reg=0x84
Mar 09 09:28:04.073 CPU0: PCI: write request (data=0x00000007) for device 'gt96100' at pc=0x60286b4c: bus=0,device=0,function=0,reg=0x0c
Mar 09 09:28:04.073 CPU0: PCI: write request (data=0x00000007) for device 'gt96100' at pc=0x60286b50: bus=0,device=0,function=0,reg=0x0c
Mar 09 09:28:04.073 CPU0: PCI: write request (data=0x00000007) for device 'gt96100' at pc=0x60286b4c: bus=0,device=0,function=0,reg=0x8c
Mar 09 09:28:04.073 CPU0: PCI: write request (data=0x00000007) for device 'gt96100' at pc=0x60286b50: bus=0,device=0,function=0,reg=0x8c
Mar 09 09:28:04.073 CPU0: PCI: write request (data=0x00000000) for device 'gt96100' at pc=0x60286b4c: bus=0,device=0,function=0,reg=0x10
Mar 09 09:28:04.073 CPU0: PCI: write request (data=0x00000000) for device 'gt96100' at pc=0x60286b50: bus=0,device=0,function=0,reg=0x10
Mar 09 09:28:04.073 CPU0: PCI: write request (data=0x00000000) for device 'gt96100' at pc=0x60286b4c: bus=0,device=0,function=0,reg=0x90
Mar 09 09:28:04.073 CPU0: PCI: write request (data=0x00000000) for device 'gt96100' at pc=0x60286b50: bus=0,device=0,function=0,reg=0x90
Mar 09 09:28:04.073 CPU0: PCI: write request (data=0x20000000) for device 'gt96100' at pc=0x60286b4c: bus=0,device=0,function=0,reg=0x14
Mar 09 09:28:04.073 CPU0: PCI: write request (data=0x20000000) for device 'gt96100' at pc=0x60286b50: bus=0,device=0,function=0,reg=0x14
Mar 09 09:28:04.073 CPU0: PCI: write request (data=0x20000000) for device 'gt96100' at pc=0x60286b4c: bus=0,device=0,function=0,reg=0x94
Mar 09 09:28:04.073 CPU0: PCI: write request (data=0x20000000) for device 'gt96100' at pc=0x60286b50: bus=0,device=0,function=0,reg=0x94
Mar 09 09:28:04.073 CPU0: PCI: write request (data=0xc0000000) for unknown device at pc=0x60286b4c (bus=0,device=0,function=1,reg=0x10).
Mar 09 09:28:04.073 CPU0: PCI: write request (data=0xc0000000) for unknown device at pc=0x60286b50 (bus=0,device=0,function=1,reg=0x10).
Mar 09 09:28:04.073 CPU0: PCI: write request (data=0xc0000000) for unknown device at pc=0x60286b4c (bus=0,device=0,function=1,reg=0x90).
Mar 09 09:28:04.073 CPU0: PCI: write request (data=0xc0000000) for unknown device at pc=0x60286b50 (bus=0,device=0,function=1,reg=0x90).
Mar 09 09:28:04.073 CPU0: PCI: write request (data=0xe0000000) for unknown device at pc=0x60286b4c (bus=0,device=0,function=1,reg=0x14).
Mar 09 09:28:04.073 CPU0: PCI: write request (data=0xe0000000) for unknown device at pc=0x60286b50 (bus=0,device=0,function=1,reg=0x14).
Mar 09 09:28:04.073 CPU0: PCI: write request (data=0xe0000000) for unknown device at pc=0x60286b4c (bus=0,device=0,function=1,reg=0x94).
Mar 09 09:28:04.073 CPU0: PCI: write request (data=0xe0000000) for unknown device at pc=0x60286b50 (bus=0,device=0,function=1,reg=0x94).
Mar 09 09:28:04.074 CPU0: IO_FPGA: write to unknown addr 0x4c, value=0xf000, pc=0x6028436c (size=2)
Mar 09 09:28:04.074 CPU0: PCI: read request for device 'ti2050b' at pc=0x60286c60: bus=0,device=1,function=0,reg=0x00
Mar 09 09:28:04.074 CPU0: PCI: read request for device 'ti2050b' at pc=0x60286c64: bus=0,device=1,function=0,reg=0x00
Mar 09 09:28:04.074 CPU0: PCI: read request for device 'ti2050b' at pc=0x60286c60: bus=0,device=1,function=0,reg=0x40
Mar 09 09:28:04.074 CPU0: PCI: read request for device 'ti2050b' at pc=0x60286c64: bus=0,device=1,function=0,reg=0x40
Mar 09 09:28:04.074 CPU0: PCI: write request (data=0xffff0000) for device 'ti2050b' at pc=0x60286b2c: bus=0,device=1,function=0,reg=0x04
Mar 09 09:28:04.074 CPU0: PCI: write request (data=0xffff0000) for device 'ti2050b' at pc=0x60286b38: bus=0,device=1,function=0,reg=0x04
Mar 09 09:28:04.074 CPU0: PCI: write request (data=0x0000f810) for device 'ti2050b' at pc=0x60286b2c: bus=0,device=1,function=0,reg=0x0c
Mar 09 09:28:04.074 CPU0: PCI: write request (data=0x0000f810) for device 'ti2050b' at pc=0x60286b38: bus=0,device=1,function=0,reg=0x0c
Mar 09 09:28:04.074 CPU0: PCI: write request (data=0x00040100) for device 'ti2050b' at pc=0x60286b2c: bus=0,device=1,function=0,reg=0x18
Mar 09 09:28:04.074 PCI: PCI bridge 0,1,0 -> pri: 00, sec: 01, sub: 04
Mar 09 09:28:04.074 CPU0: PCI: write request (data=0x00040100) for device 'ti2050b' at pc=0x60286b38: bus=0,device=1,function=0,reg=0x18
Mar 09 09:28:04.074 PCI: PCI bridge 0,1,0 -> pri: 00, sec: 01, sub: 04
Mar 09 09:28:04.074 CPU0: PCI: write request (data=0x02801f00) for device 'ti2050b' at pc=0x60286b2c: bus=0,device=1,function=0,reg=0x1c
Mar 09 09:28:04.074 CPU0: PCI: write request (data=0x02801f00) for device 'ti2050b' at pc=0x60286b38: bus=0,device=1,function=0,reg=0x1c
Mar 09 09:28:04.074 CPU0: PCI: write request (data=0x4d704d00) for device 'ti2050b' at pc=0x60286b2c: bus=0,device=1,function=0,reg=0x20
Mar 09 09:28:04.074 CPU0: PCI: write request (data=0x4d704d00) for device 'ti2050b' at pc=0x60286b38: bus=0,device=1,function=0,reg=0x20
Mar 09 09:28:04.074 CPU0: PCI: write request (data=0x00014d01) for device 'ti2050b' at pc=0x60286b2c: bus=0,device=1,function=0,reg=0x24
Mar 09 09:28:04.074 CPU0: PCI: write request (data=0x00014d01) for device 'ti2050b' at pc=0x60286b38: bus=0,device=1,function=0,reg=0x24
Mar 09 09:28:04.074 CPU0: PCI: write request (data=0x00200020) for device 'ti2050b' at pc=0x60286b2c: bus=0,device=1,function=0,reg=0x30
Mar 09 09:28:04.074 CPU0: PCI: write request (data=0x00200020) for device 'ti2050b' at pc=0x60286b38: bus=0,device=1,function=0,reg=0x30
Mar 09 09:28:04.074 CPU0: PCI: write request (data=0x03000000) for device 'ti2050b' at pc=0x60286b2c: bus=0,device=1,function=0,reg=0x3c
Mar 09 09:28:04.074 CPU0: PCI: write request (data=0x03000000) for device 'ti2050b' at pc=0x60286b38: bus=0,device=1,function=0,reg=0x3c
Mar 09 09:28:04.074 CPU0: PCI: write request (data=0x00000000) for device 'ti2050b' at pc=0x60286b2c: bus=0,device=1,function=0,reg=0x40
Mar 09 09:28:04.074 CPU0: PCI: write request (data=0x00000000) for device 'ti2050b' at pc=0x60286b38: bus=0,device=1,function=0,reg=0x40
Mar 09 09:28:04.074 CPU0: PCI: write request (data=0x00000000) for device 'ti2050b' at pc=0x60286b2c: bus=0,device=1,function=0,reg=0x64
Mar 09 09:28:04.074 CPU0: PCI: write request (data=0x00000000) for device 'ti2050b' at pc=0x60286b38: bus=0,device=1,function=0,reg=0x64
Mar 09 09:28:04.074 CPU0: PCI: write request (data=0x00000000) for device 'ti2050b' at pc=0x60286b2c: bus=0,device=1,function=0,reg=0x68
Mar 09 09:28:04.074 CPU0: PCI: write request (data=0x00000000) for device 'ti2050b' at pc=0x60286b38: bus=0,device=1,function=0,reg=0x68
Mar 09 09:28:04.074 CPU0: PCI: write request (data=0x00000007) for device 'ti2050b' at pc=0x60286b2c: bus=0,device=1,function=0,reg=0x04
Mar 09 09:28:04.075 CPU0: PCI: write request (data=0x00000007) for device 'ti2050b' at pc=0x60286b38: bus=0,device=1,function=0,reg=0x04
Mar 09 09:28:04.075 CPU0: PCI: write request (data=0x00000001) for device 'ti2050b' at pc=0x60286b2c: bus=0,device=1,function=0,reg=0xf0
Mar 09 09:28:04.075 CPU0: PCI: write request (data=0x00000001) for device 'ti2050b' at pc=0x60286b38: bus=0,device=1,function=0,reg=0xf0
Mar 09 09:28:04.075 CPU0: PCI: read request for device 'ti2050b' at pc=0x60286c60: bus=0,device=2,function=0,reg=0x00
Mar 09 09:28:04.075 CPU0: PCI: read request for device 'ti2050b' at pc=0x60286c64: bus=0,device=2,function=0,reg=0x00
Mar 09 09:28:04.075 CPU0: PCI: read request for device 'ti2050b' at pc=0x60286c60: bus=0,device=2,function=0,reg=0x40
Mar 09 09:28:04.075 CPU0: PCI: read request for device 'ti2050b' at pc=0x60286c64: bus=0,device=2,function=0,reg=0x40
Mar 09 09:28:04.075 CPU0: PCI: write request (data=0xffff0000) for device 'ti2050b' at pc=0x60286b2c: bus=0,device=2,function=0,reg=0x04
Mar 09 09:28:04.075 CPU0: PCI: write request (data=0xffff0000) for device 'ti2050b' at pc=0x60286b38: bus=0,device=2,function=0,reg=0x04
Mar 09 09:28:04.075 CPU0: PCI: write request (data=0x0000f810) for device 'ti2050b' at pc=0x60286b2c: bus=0,device=2,function=0,reg=0x0c
Mar 09 09:28:04.075 CPU0: PCI: write request (data=0x0000f810) for device 'ti2050b' at pc=0x60286b38: bus=0,device=2,function=0,reg=0x0c
Mar 09 09:28:04.075 CPU0: PCI: write request (data=0x00080500) for device 'ti2050b' at pc=0x60286b2c: bus=0,device=2,function=0,reg=0x18
Mar 09 09:28:04.075 PCI: PCI bridge 0,2,0 -> pri: 00, sec: 05, sub: 08
Mar 09 09:28:04.075 CPU0: PCI: write request (data=0x00080500) for device 'ti2050b' at pc=0x60286b38: bus=0,device=2,function=0,reg=0x18
Mar 09 09:28:04.075 PCI: PCI bridge 0,2,0 -> pri: 00, sec: 05, sub: 08
Mar 09 09:28:04.075 CPU0: PCI: write request (data=0x02803f20) for device 'ti2050b' at pc=0x60286b2c: bus=0,device=2,function=0,reg=0x1c
Mar 09 09:28:04.075 CPU0: PCI: write request (data=0x02803f20) for device 'ti2050b' at pc=0x60286b38: bus=0,device=2,function=0,reg=0x1c
Mar 09 09:28:04.075 CPU0: PCI: write request (data=0x4df04d80) for device 'ti2050b' at pc=0x60286b2c: bus=0,device=2,function=0,reg=0x20
Mar 09 09:28:04.075 CPU0: PCI: write request (data=0x4df04d80) for device 'ti2050b' at pc=0x60286b38: bus=0,device=2,function=0,reg=0x20
Mar 09 09:28:04.075 CPU0: PCI: write request (data=0x00014d81) for device 'ti2050b' at pc=0x60286b2c: bus=0,device=2,function=0,reg=0x24
Mar 09 09:28:04.075 CPU0: PCI: write request (data=0x00014d81) for device 'ti2050b' at pc=0x60286b38: bus=0,device=2,function=0,reg=0x24
Mar 09 09:28:04.075 CPU0: PCI: write request (data=0x00200020) for device 'ti2050b' at pc=0x60286b2c: bus=0,device=2,function=0,reg=0x30
Mar 09 09:28:04.075 CPU0: PCI: write request (data=0x00200020) for device 'ti2050b' at pc=0x60286b38: bus=0,device=2,function=0,reg=0x30
Mar 09 09:28:04.075 CPU0: PCI: write request (data=0x03000000) for device 'ti2050b' at pc=0x60286b2c: bus=0,device=2,function=0,reg=0x3c
Mar 09 09:28:04.075 CPU0: PCI: write request (data=0x03000000) for device 'ti2050b' at pc=0x60286b38: bus=0,device=2,function=0,reg=0x3c
Mar 09 09:28:04.075 CPU0: PCI: write request (data=0x00000000) for device 'ti2050b' at pc=0x60286b2c: bus=0,device=2,function=0,reg=0x40
Mar 09 09:28:04.075 CPU0: PCI: write request (data=0x00000000) for device 'ti2050b' at pc=0x60286b38: bus=0,device=2,function=0,reg=0x40
Mar 09 09:28:04.075 CPU0: PCI: write request (data=0x00000000) for device 'ti2050b' at pc=0x60286b2c: bus=0,device=2,function=0,reg=0x64
Mar 09 09:28:04.075 CPU0: PCI: write request (data=0x00000000) for device 'ti2050b' at pc=0x60286b38: bus=0,device=2,function=0,reg=0x64
Mar 09 09:28:04.075 CPU0: PCI: write request (data=0x00000000) for device 'ti2050b' at pc=0x60286b2c: bus=0,device=2,function=0,reg=0x68
Mar 09 09:28:04.075 CPU0: PCI: write request (data=0x00000000) for device 'ti2050b' at pc=0x60286b38: bus=0,device=2,function=0,reg=0x68
Mar 09 09:28:04.075 CPU0: PCI: write request (data=0x00000007) for device 'ti2050b' at pc=0x60286b2c: bus=0,device=2,function=0,reg=0x04
Mar 09 09:28:04.075 CPU0: PCI: write request (data=0x00000007) for device 'ti2050b' at pc=0x60286b38: bus=0,device=2,function=0,reg=0x04
Mar 09 09:28:04.075 CPU0: PCI: write request (data=0x00000001) for device 'ti2050b' at pc=0x60286b2c: bus=0,device=2,function=0,reg=0xf0
Mar 09 09:28:04.075 CPU0: PCI: write request (data=0x00000001) for device 'ti2050b' at pc=0x60286b38: bus=0,device=2,function=0,reg=0xf0
Mar 09 09:28:04.075 CPU0: PCI: read request for device 'ti2050b' at pc=0x60286c60: bus=0,device=3,function=0,reg=0x00
Mar 09 09:28:04.075 CPU0: PCI: read request for device 'ti2050b' at pc=0x60286c64: bus=0,device=3,function=0,reg=0x00
Mar 09 09:28:04.075 CPU0: PCI: read request for device 'ti2050b' at pc=0x60286c60: bus=0,device=3,function=0,reg=0x40
Mar 09 09:28:04.075 CPU0: PCI: read request for device 'ti2050b' at pc=0x60286c64: bus=0,device=3,function=0,reg=0x40
Mar 09 09:28:04.075 CPU0: PCI: write request (data=0xffff0000) for device 'ti2050b' at pc=0x60286b2c: bus=0,device=3,function=0,reg=0x04
Mar 09 09:28:04.075 CPU0: PCI: write request (data=0xffff0000) for device 'ti2050b' at pc=0x60286b38: bus=0,device=3,function=0,reg=0x04
Mar 09 09:28:04.075 CPU0: PCI: write request (data=0x0000f810) for device 'ti2050b' at pc=0x60286b2c: bus=0,device=3,function=0,reg=0x0c
Mar 09 09:28:04.075 CPU0: PCI: write request (data=0x0000f810) for device 'ti2050b' at pc=0x60286b38: bus=0,device=3,function=0,reg=0x0c
Mar 09 09:28:04.075 CPU0: PCI: write request (data=0x000c0900) for device 'ti2050b' at pc=0x60286b2c: bus=0,device=3,function=0,reg=0x18
Mar 09 09:28:04.075 PCI: PCI bridge 0,3,0 -> pri: 00, sec: 09, sub: 12
Mar 09 09:28:04.075 CPU0: PCI: write request (data=0x000c0900) for device 'ti2050b' at pc=0x60286b38: bus=0,device=3,function=0,reg=0x18
Mar 09 09:28:04.075 PCI: PCI bridge 0,3,0 -> pri: 00, sec: 09, sub: 12
Mar 09 09:28:04.075 CPU0: PCI: write request (data=0x02809f80) for device 'ti2050b' at pc=0x60286b2c: bus=0,device=3,function=0,reg=0x1c
Mar 09 09:28:04.075 CPU0: PCI: write request (data=0x02809f80) for device 'ti2050b' at pc=0x60286b38: bus=0,device=3,function=0,reg=0x1c
Mar 09 09:28:04.075 CPU0: PCI: write request (data=0x4e704e00) for device 'ti2050b' at pc=0x60286b2c: bus=0,device=3,function=0,reg=0x20
Mar 09 09:28:04.075 CPU0: PCI: write request (data=0x4e704e00) for device 'ti2050b' at pc=0x60286b38: bus=0,device=3,function=0,reg=0x20
Mar 09 09:28:04.075 CPU0: PCI: write request (data=0x00014e01) for device 'ti2050b' at pc=0x60286b2c: bus=0,device=3,function=0,reg=0x24
Mar 09 09:28:04.075 CPU0: PCI: write request (data=0x00014e01) for device 'ti2050b' at pc=0x60286b38: bus=0,device=3,function=0,reg=0x24
Mar 09 09:28:04.075 CPU0: PCI: write request (data=0x00200020) for device 'ti2050b' at pc=0x60286b2c: bus=0,device=3,function=0,reg=0x30
Mar 09 09:28:04.075 CPU0: PCI: write request (data=0x00200020) for device 'ti2050b' at pc=0x60286b38: bus=0,device=3,function=0,reg=0x30
Mar 09 09:28:04.075 CPU0: PCI: write request (data=0x03000000) for device 'ti2050b' at pc=0x60286b2c: bus=0,device=3,function=0,reg=0x3c
Mar 09 09:28:04.075 CPU0: PCI: write request (data=0x03000000) for device 'ti2050b' at pc=0x60286b38: bus=0,device=3,function=0,reg=0x3c
Mar 09 09:28:04.076 CPU0: PCI: write request (data=0x00000000) for device 'ti2050b' at pc=0x60286b2c: bus=0,device=3,function=0,reg=0x40
Mar 09 09:28:04.076 CPU0: PCI: write request (data=0x00000000) for device 'ti2050b' at pc=0x60286b38: bus=0,device=3,function=0,reg=0x40
Mar 09 09:28:04.076 CPU0: PCI: write request (data=0x00000000) for device 'ti2050b' at pc=0x60286b2c: bus=0,device=3,function=0,reg=0x64
Mar 09 09:28:04.076 CPU0: PCI: write request (data=0x00000000) for device 'ti2050b' at pc=0x60286b38: bus=0,device=3,function=0,reg=0x64
Mar 09 09:28:04.076 CPU0: PCI: write request (data=0x00000000) for device 'ti2050b' at pc=0x60286b2c: bus=0,device=3,function=0,reg=0x68
Mar 09 09:28:04.076 CPU0: PCI: write request (data=0x00000000) for device 'ti2050b' at pc=0x60286b38: bus=0,device=3,function=0,reg=0x68
Mar 09 09:28:04.076 CPU0: PCI: write request (data=0x00000007) for device 'ti2050b' at pc=0x60286b2c: bus=0,device=3,function=0,reg=0x04
Mar 09 09:28:04.076 CPU0: PCI: write request (data=0x00000007) for device 'ti2050b' at pc=0x60286b38: bus=0,device=3,function=0,reg=0x04
Mar 09 09:28:04.076 CPU0: PCI: write request (data=0x00000001) for device 'ti2050b' at pc=0x60286b2c: bus=0,device=3,function=0,reg=0xf0
Mar 09 09:28:04.076 CPU0: PCI: write request (data=0x00000001) for device 'ti2050b' at pc=0x60286b38: bus=0,device=3,function=0,reg=0xf0
Mar 09 09:28:04.076 CPU0: PCI: read request for device 'ti2050b' at pc=0x60286c60: bus=0,device=4,function=0,reg=0x00
Mar 09 09:28:04.076 CPU0: PCI: read request for device 'ti2050b' at pc=0x60286c64: bus=0,device=4,function=0,reg=0x00
Mar 09 09:28:04.076 CPU0: PCI: read request for device 'ti2050b' at pc=0x60286c60: bus=0,device=4,function=0,reg=0x40
Mar 09 09:28:04.076 CPU0: PCI: read request for device 'ti2050b' at pc=0x60286c64: bus=0,device=4,function=0,reg=0x40
Mar 09 09:28:04.076 CPU0: PCI: write request (data=0xffff0000) for device 'ti2050b' at pc=0x60286b2c: bus=0,device=4,function=0,reg=0x04
Mar 09 09:28:04.076 CPU0: PCI: write request (data=0xffff0000) for device 'ti2050b' at pc=0x60286b38: bus=0,device=4,function=0,reg=0x04
Mar 09 09:28:04.076 CPU0: PCI: write request (data=0x0000f810) for device 'ti2050b' at pc=0x60286b2c: bus=0,device=4,function=0,reg=0x0c
Mar 09 09:28:04.076 CPU0: PCI: write request (data=0x0000f810) for device 'ti2050b' at pc=0x60286b38: bus=0,device=4,function=0,reg=0x0c
Mar 09 09:28:04.076 CPU0: PCI: write request (data=0x00100d00) for device 'ti2050b' at pc=0x60286b2c: bus=0,device=4,function=0,reg=0x18
Mar 09 09:28:04.076 PCI: PCI bridge 0,4,0 -> pri: 00, sec: 13, sub: 16
Mar 09 09:28:04.076 CPU0: PCI: write request (data=0x00100d00) for device 'ti2050b' at pc=0x60286b38: bus=0,device=4,function=0,reg=0x18
Mar 09 09:28:04.076 PCI: PCI bridge 0,4,0 -> pri: 00, sec: 13, sub: 16
Mar 09 09:28:04.076 CPU0: PCI: write request (data=0x0280bfa0) for device 'ti2050b' at pc=0x60286b2c: bus=0,device=4,function=0,reg=0x1c
Mar 09 09:28:04.076 CPU0: PCI: write request (data=0x0280bfa0) for device 'ti2050b' at pc=0x60286b38: bus=0,device=4,function=0,reg=0x1c
Mar 09 09:28:04.076 CPU0: PCI: write request (data=0x4ef04e80) for device 'ti2050b' at pc=0x60286b2c: bus=0,device=4,function=0,reg=0x20
Mar 09 09:28:04.076 CPU0: PCI: write request (data=0x4ef04e80) for device 'ti2050b' at pc=0x60286b38: bus=0,device=4,function=0,reg=0x20
Mar 09 09:28:04.076 CPU0: PCI: write request (data=0x00014e81) for device 'ti2050b' at pc=0x60286b2c: bus=0,device=4,function=0,reg=0x24
Mar 09 09:28:04.076 CPU0: PCI: write request (data=0x00014e81) for device 'ti2050b' at pc=0x60286b38: bus=0,device=4,function=0,reg=0x24
Mar 09 09:28:04.076 CPU0: PCI: write request (data=0x00200020) for device 'ti2050b' at pc=0x60286b2c: bus=0,device=4,function=0,reg=0x30
Mar 09 09:28:04.076 CPU0: PCI: write request (data=0x00200020) for device 'ti2050b' at pc=0x60286b38: bus=0,device=4,function=0,reg=0x30
Mar 09 09:28:04.076 CPU0: PCI: write request (data=0x03000000) for device 'ti2050b' at pc=0x60286b2c: bus=0,device=4,function=0,reg=0x3c
Mar 09 09:28:04.076 CPU0: PCI: write request (data=0x03000000) for device 'ti2050b' at pc=0x60286b38: bus=0,device=4,function=0,reg=0x3c
Mar 09 09:28:04.076 CPU0: PCI: write request (data=0x00000000) for device 'ti2050b' at pc=0x60286b2c: bus=0,device=4,function=0,reg=0x40
Mar 09 09:28:04.076 CPU0: PCI: write request (data=0x00000000) for device 'ti2050b' at pc=0x60286b38: bus=0,device=4,function=0,reg=0x40
Mar 09 09:28:04.076 CPU0: PCI: write request (data=0x00000000) for device 'ti2050b' at pc=0x60286b2c: bus=0,device=4,function=0,reg=0x64
Mar 09 09:28:04.076 CPU0: PCI: write request (data=0x00000000) for device 'ti2050b' at pc=0x60286b38: bus=0,device=4,function=0,reg=0x64
Mar 09 09:28:04.076 CPU0: PCI: write request (data=0x00000000) for device 'ti2050b' at pc=0x60286b2c: bus=0,device=4,function=0,reg=0x68
Mar 09 09:28:04.076 CPU0: PCI: write request (data=0x00000000) for device 'ti2050b' at pc=0x60286b38: bus=0,device=4,function=0,reg=0x68
Mar 09 09:28:04.076 CPU0: PCI: write request (data=0x00000007) for device 'ti2050b' at pc=0x60286b2c: bus=0,device=4,function=0,reg=0x04
Mar 09 09:28:04.076 CPU0: PCI: write request (data=0x00000007) for device 'ti2050b' at pc=0x60286b38: bus=0,device=4,function=0,reg=0x04
Mar 09 09:28:04.076 CPU0: PCI: write request (data=0x00000001) for device 'ti2050b' at pc=0x60286b2c: bus=0,device=4,function=0,reg=0xf0
Mar 09 09:28:04.076 CPU0: PCI: write request (data=0x00000001) for device 'ti2050b' at pc=0x60286b38: bus=0,device=4,function=0,reg=0xf0
Mar 09 09:28:04.076 CPU0: PCI: write request (data=0x24000000) for device 'gt96100' at pc=0x60286b4c: bus=0,device=0,function=0,reg=0x20
Mar 09 09:28:04.076 CPU0: PCI: write request (data=0x24000000) for device 'gt96100' at pc=0x60286b50: bus=0,device=0,function=0,reg=0x20
Mar 09 09:28:04.076 CPU0: PCI: write request (data=0x24000000) for device 'gt96100' at pc=0x60286b4c: bus=0,device=0,function=0,reg=0xa0
Mar 09 09:28:04.076 CPU0: PCI: write request (data=0x24000000) for device 'gt96100' at pc=0x60286b50: bus=0,device=0,function=0,reg=0xa0
Mar 09 09:28:04.076 CPU0: IO_FPGA: read from unknown addr 0x16, pc=0x60276b14 (size=2)
Mar 09 09:28:07.723 ROM: unhandled syscall 0x0000003e at pc=0x60a9e9bc (a1=0x80007d9c,a2=0x00002580,a3=0x64590000)
Mar 09 09:28:07.723 ROM: unhandled syscall 0x00000047 at pc=0x60a9e9bc (a1=0x80007da4,a2=0x00000000,a3=0x64590000)
Mar 09 09:28:08.810 CPU0: JIT: partial JIT flush (count=178)
Mar 09 09:28:08.880 CPU0: JIT: flushing data structures (compiled pages=234)
Mar 09 09:28:08.941 ROM: trying to read bootvar 'BOOT'
Mar 09 09:28:08.941 ROM: trying to read bootvar 'CONFIG_FILE'
Mar 09 09:28:08.941 ROM: trying to read bootvar 'BOOTLDR'
Mar 09 09:28:08.941 ROM: trying to read bootvar 'RSHELF'
Mar 09 09:28:08.941 ROM: trying to read bootvar 'DSHELF'
Mar 09 09:28:08.941 ROM: trying to read bootvar 'DSHELFINFO'
Mar 09 09:28:08.941 ROM: trying to read bootvar 'RESET_COUNTER'
Mar 09 09:28:08.942 ROM: trying to read bootvar 'CHRG_LOCRECSN'
Mar 09 09:28:08.942 ROM: trying to read bootvar 'CHRG_ID'
Mar 09 09:28:08.942 ROM: trying to read bootvar 'SLOTCACHE'
Mar 09 09:28:08.942 ROM: trying to read bootvar 'OVERTEMP'
Mar 09 09:28:08.942 ROM: trying to read bootvar 'DIAG'
Mar 09 09:28:08.942 ROM: trying to read bootvar 'WARM_REBOOT'
Mar 09 09:28:08.972 CPU0: JIT: partial JIT flush (count=179)
Mar 09 09:28:09.148 CPU0: JIT: flushing data structures (compiled pages=242)
Mar 09 09:28:09.256 CPU0: IO_FPGA: read from unknown addr 0x16, pc=0x60819334 (size=2)
Mar 09 09:28:09.256 CPU0: MTS: read  access to undefined address 0x3c080022 at pc=0x60818f30 (size=1)
Mar 09 09:28:09.256 CPU0: MTS: read  access to undefined address 0x3c08002b at pc=0x60818f74 (size=1)
Mar 09 09:28:09.256 CPU0: MTS: write access to undefined address 0x3c08002b at pc=0x60818f80, value=0x00000020 (size=1)
Mar 09 09:28:09.256 CPU0: MTS: read  access to undefined address 0x3c08002b at pc=0x60818f84 (size=1)
Mar 09 09:28:09.256 CPU0: MTS: write access to undefined address 0x3c08002b at pc=0x60818f8c, value=0x00000000 (size=1)
Mar 09 09:28:09.257 CPU0: MTS: read  access to undefined address 0x3c08002b at pc=0x60818f98 (size=1)
Mar 09 09:28:09.257 CPU0: MTS: write access to undefined address 0x3c08002b at pc=0x60818fa4, value=0x00000040 (size=1)
Mar 09 09:28:09.257 CPU0: MTS: read  access to undefined address 0x3c080023 at pc=0x60818fb8 (size=1)
Mar 09 09:28:09.257 CPU0: MTS: write access to undefined address 0x3c080023 at pc=0x60818fc4, value=0x00000000 (size=1)
Mar 09 09:28:09.257 CPU0: MTS: read  access to undefined address 0x3c080023 at pc=0x60818fd0 (size=1)
Mar 09 09:28:09.257 CPU0: MTS: write access to undefined address 0x3c080023 at pc=0x60818fe0, value=0x00000080 (size=1)
Mar 09 09:28:09.257 CPU0: MTS: read  access to undefined address 0x3c000002 at pc=0x6081adac (size=1)
Mar 09 09:28:09.257 CPU0: MTS: write access to undefined address 0x3c000002 at pc=0x6081adb8, value=0x00000080 (size=1)
Mar 09 09:28:09.257 CPU0: MTS: read  access to undefined address 0x3c000002 at pc=0x6081adbc (size=1)
Mar 09 09:28:09.420 CPU0: MTS: read  access to undefined address 0x3c000002 at pc=0x6081ade4 (size=1)
Mar 09 09:28:09.583 CPU0: MTS: read  access to undefined address 0x3c000002 at pc=0x6081ade4 (size=1)
Mar 09 09:28:09.719 CPU0: MTS: read  access to undefined address 0x3c000002 at pc=0x6081ade4 (size=1)
Mar 09 09:28:09.854 CPU0: MTS: read  access to undefined address 0x3c000002 at pc=0x6081ade4 (size=1)
Mar 09 09:28:10.012 CPU0: MTS: read  access to undefined address 0x3c000002 at pc=0x6081ade4 (size=1)
Mar 09 09:28:10.143 CPU0: MTS: read  access to undefined address 0x3c000002 at pc=0x6081ade4 (size=1)
Mar 09 09:28:10.143 CPU0: MTS: write access to undefined address 0x3c080007 at pc=0x608190cc, value=0x00000002 (size=1)
Mar 09 09:28:10.143 CPU0: MTS: write access to undefined address 0x3c080008 at pc=0x608190d4, value=0x00000002 (size=1)
Mar 09 09:28:10.143 CPU0: MTS: write access to undefined address 0x3c080009 at pc=0x608190dc, value=0x00000002 (size=1)
Mar 09 09:28:10.143 CPU0: MTS: write access to undefined address 0x3c08000a at pc=0x608190e0, value=0x00000002 (size=1)
Mar 09 09:28:10.143 CPU0: MTS: write access to undefined address 0x3c08000b at pc=0x608190e4, value=0x00000002 (size=1)
Mar 09 09:28:10.143 CPU0: MTS: write access to undefined address 0x3c08000c at pc=0x608190e8, value=0x00000002 (size=1)
Mar 09 09:28:10.143 CPU0: MTS: read  access to undefined address 0x3c080022 at pc=0x60819f6c (size=1)
Mar 09 09:28:10.211 CPU0: JIT: partial JIT flush (count=187)
Mar 09 09:28:10.277 CPU0: JIT: flushing data structures (compiled pages=253)
Mar 09 09:28:10.359 CPU0: IO_FPGA: read from unknown addr 0x10000a, pc=0x60283dd4 (size=2)
Mar 09 09:28:10.359 CPU0: IO_FPGA: write to unknown addr 0x10000a, value=0x1000, pc=0x60283ddc (size=2)
Mar 09 09:28:10.645 CPU0: PCI: read request for device 'ti2050b' at pc=0x60286c60: bus=0,device=1,function=0,reg=0x3c
Mar 09 09:28:10.645 CPU0: PCI: read request for device 'ti2050b' at pc=0x60286c64: bus=0,device=1,function=0,reg=0x3c
Mar 09 09:28:10.645 CPU0: PCI: write request (data=0x00400000) for device 'ti2050b' at pc=0x60286b2c: bus=0,device=1,function=0,reg=0x3c
Mar 09 09:28:10.645 CPU0: PCI: write request (data=0x00400000) for device 'ti2050b' at pc=0x60286b38: bus=0,device=1,function=0,reg=0x3c
Mar 09 09:28:10.645 CPU0: PCI: read request for device 'ti2050b' at pc=0x60286c60: bus=0,device=1,function=0,reg=0x3c
Mar 09 09:28:10.645 CPU0: PCI: read request for device 'ti2050b' at pc=0x60286c64: bus=0,device=1,function=0,reg=0x3c
Mar 09 09:28:10.645 CPU0: PCI: write request (data=0x00000000) for device 'ti2050b' at pc=0x60286b2c: bus=0,device=1,function=0,reg=0x3c
Mar 09 09:28:10.645 CPU0: PCI: write request (data=0x00000000) for device 'ti2050b' at pc=0x60286b38: bus=0,device=1,function=0,reg=0x3c
Mar 09 09:28:10.779 CPU0: PCI: read request for device 'ti2050b' at pc=0x60286c60: bus=0,device=1,function=0,reg=0x00
Mar 09 09:28:10.779 CPU0: PCI: read request for device 'ti2050b' at pc=0x60286c64: bus=0,device=1,function=0,reg=0x00
Mar 09 09:28:10.779 CPU0: PCI: read request for device 'ti2050b' at pc=0x60286c60: bus=0,device=1,function=0,reg=0x40
Mar 09 09:28:10.779 CPU0: PCI: read request for device 'ti2050b' at pc=0x60286c64: bus=0,device=1,function=0,reg=0x40
Mar 09 09:28:10.779 CPU0: PCI: write request (data=0xffff0000) for device 'ti2050b' at pc=0x60286b2c: bus=0,device=1,function=0,reg=0x04
Mar 09 09:28:10.779 CPU0: PCI: write request (data=0xffff0000) for device 'ti2050b' at pc=0x60286b38: bus=0,device=1,function=0,reg=0x04
Mar 09 09:28:10.779 CPU0: PCI: write request (data=0x0000f810) for device 'ti2050b' at pc=0x60286b2c: bus=0,device=1,function=0,reg=0x0c
Mar 09 09:28:10.779 CPU0: PCI: write request (data=0x0000f810) for device 'ti2050b' at pc=0x60286b38: bus=0,device=1,function=0,reg=0x0c
Mar 09 09:28:10.779 CPU0: PCI: write request (data=0x00040100) for device 'ti2050b' at pc=0x60286b2c: bus=0,device=1,function=0,reg=0x18
Mar 09 09:28:10.779 PCI: PCI bridge 0,1,0 -> pri: 00, sec: 01, sub: 04
Mar 09 09:28:10.779 CPU0: PCI: write request (data=0x00040100) for device 'ti2050b' at pc=0x60286b38: bus=0,device=1,function=0,reg=0x18
Mar 09 09:28:10.779 PCI: PCI bridge 0,1,0 -> pri: 00, sec: 01, sub: 04
Mar 09 09:28:10.779 CPU0: PCI: write request (data=0x02801f00) for device 'ti2050b' at pc=0x60286b2c: bus=0,device=1,function=0,reg=0x1c
Mar 09 09:28:10.779 CPU0: PCI: write request (data=0x02801f00) for device 'ti2050b' at pc=0x60286b38: bus=0,device=1,function=0,reg=0x1c
Mar 09 09:28:10.779 CPU0: PCI: write request (data=0x4d704d00) for device 'ti2050b' at pc=0x60286b2c: bus=0,device=1,function=0,reg=0x20
Mar 09 09:28:10.779 CPU0: PCI: write request (data=0x4d704d00) for device 'ti2050b' at pc=0x60286b38: bus=0,device=1,function=0,reg=0x20
Mar 09 09:28:10.779 CPU0: PCI: write request (data=0x00014d01) for device 'ti2050b' at pc=0x60286b2c: bus=0,device=1,function=0,reg=0x24
Mar 09 09:28:10.780 CPU0: PCI: write request (data=0x00014d01) for device 'ti2050b' at pc=0x60286b38: bus=0,device=1,function=0,reg=0x24
Mar 09 09:28:10.780 CPU0: PCI: write request (data=0x00200020) for device 'ti2050b' at pc=0x60286b2c: bus=0,device=1,function=0,reg=0x30
Mar 09 09:28:10.780 CPU0: PCI: write request (data=0x00200020) for device 'ti2050b' at pc=0x60286b38: bus=0,device=1,function=0,reg=0x30
Mar 09 09:28:10.780 CPU0: PCI: write request (data=0x03000000) for device 'ti2050b' at pc=0x60286b2c: bus=0,device=1,function=0,reg=0x3c
Mar 09 09:28:10.780 CPU0: PCI: write request (data=0x03000000) for device 'ti2050b' at pc=0x60286b38: bus=0,device=1,function=0,reg=0x3c
Mar 09 09:28:10.780 CPU0: PCI: write request (data=0x00000000) for device 'ti2050b' at pc=0x60286b2c: bus=0,device=1,function=0,reg=0x40
Mar 09 09:28:10.780 CPU0: PCI: write request (data=0x00000000) for device 'ti2050b' at pc=0x60286b38: bus=0,device=1,function=0,reg=0x40
Mar 09 09:28:10.780 CPU0: PCI: write request (data=0x00000000) for device 'ti2050b' at pc=0x60286b2c: bus=0,device=1,function=0,reg=0x64
Mar 09 09:28:10.780 CPU0: PCI: write request (data=0x00000000) for device 'ti2050b' at pc=0x60286b38: bus=0,device=1,function=0,reg=0x64
Mar 09 09:28:10.780 CPU0: PCI: write request (data=0x00000000) for device 'ti2050b' at pc=0x60286b2c: bus=0,device=1,function=0,reg=0x68
Mar 09 09:28:10.780 CPU0: PCI: write request (data=0x00000000) for device 'ti2050b' at pc=0x60286b38: bus=0,device=1,function=0,reg=0x68
Mar 09 09:28:10.780 CPU0: PCI: write request (data=0x00000007) for device 'ti2050b' at pc=0x60286b2c: bus=0,device=1,function=0,reg=0x04
Mar 09 09:28:10.780 CPU0: PCI: write request (data=0x00000007) for device 'ti2050b' at pc=0x60286b38: bus=0,device=1,function=0,reg=0x04
Mar 09 09:28:10.780 CPU0: PCI: write request (data=0x00000001) for device 'ti2050b' at pc=0x60286b2c: bus=0,device=1,function=0,reg=0xf0
Mar 09 09:28:10.780 CPU0: PCI: write request (data=0x00000001) for device 'ti2050b' at pc=0x60286b38: bus=0,device=1,function=0,reg=0xf0
Mar 09 09:28:11.029 CPU0: JIT: partial JIT flush (count=175)
Mar 09 09:28:11.205 CPU0: MTS: read  access to undefined address 0x3c080004 at pc=0x60678648 (size=1)
Mar 09 09:28:11.205 CPU0: MTS: write access to undefined address 0x3c080004 at pc=0x60678650, value=0x00000004 (size=1)
Mar 09 09:28:11.211 CPU0: MTS: read  access to undefined address 0x3c080001 at pc=0x6069ce5c (size=1)
Mar 09 09:28:11.211 CPU0: MTS: write access to undefined address 0x3c080001 at pc=0x6069ce80, value=0x00000008 (size=1)
Mar 09 09:28:11.211 CPU0: MTS: read  access to undefined address 0x3c080004 at pc=0x6069cea0 (size=1)
Mar 09 09:28:11.211 CPU0: MTS: write access to undefined address 0x3c080004 at pc=0x6069cea8, value=0x00000002 (size=1)
Mar 09 09:28:11.211 CPU0: MTS: read  access to undefined address 0x3c080004 at pc=0x6069cebc (size=1)
Mar 09 09:28:11.211 CPU0: MTS: write access to undefined address 0x3c080004 at pc=0x6069cef8, value=0x00000000 (size=1)
Mar 09 09:28:11.212 CPU0: MTS: read  access to undefined address 0x3c080025 at pc=0x60676ae0 (size=1)
Mar 09 09:28:11.212 CPU0: MTS: write access to undefined address 0x3c080025 at pc=0x60676aec, value=0x00000000 (size=1)
Mar 09 09:28:11.212 CPU0: MTS: read  access to undefined address 0x3c080026 at pc=0x60676bf0 (size=1)
Mar 09 09:28:11.213 CPU0: MTS: write access to undefined address 0x3c080026 at pc=0x60676e20, value=0x00000002 (size=1)
Mar 09 09:28:11.213 CPU0: MTS: read  access to undefined address 0x3c08001f at pc=0x60676f6c (size=1)
Mar 09 09:28:11.213 CPU0: MTS: write access to undefined address 0x3c08001f at pc=0x60676f78, value=0x00000000 (size=1)
Mar 09 09:28:11.213 CPU0: MTS: read  access to undefined address 0x3c080001 at pc=0x6069cc18 (size=1)
Mar 09 09:28:11.213 CPU0: MTS: write access to undefined address 0x3c080001 at pc=0x6069cc20, value=0x00000000 (size=1)
Mar 09 09:28:11.213 CPU0: MTS: read  access to undefined address 0x3c080001 at pc=0x6069cc40 (size=1)
Mar 09 09:28:11.213 CPU0: MTS: write access to undefined address 0x3c080001 at pc=0x6069cc48, value=0x00000000 (size=1)
Mar 09 09:28:11.213 CPU0: MTS: read  access to undefined address 0x3c080001 at pc=0x6069cc5c (size=1)
Mar 09 09:28:11.213 CPU0: MTS: write access to undefined address 0x3c080001 at pc=0x6069cce8, value=0x00000004 (size=1)
Mar 09 09:28:11.213 CPU0: MTS: read  access to undefined address 0x3c08001f at pc=0x6067697c (size=1)
Mar 09 09:28:11.232 CPU0: PCI: read request for device 'NM-1FE-TX(1)' at pc=0x60286c60: bus=1,device=0,function=0,reg=0x00
Mar 09 09:28:11.233 CPU0: PCI: read request for device 'NM-1FE-TX(1)' at pc=0x60286c64: bus=1,device=0,function=0,reg=0x00
Mar 09 09:28:11.233 CPU0: PCI: read request for device 'NM-1FE-TX(1)' at pc=0x60286c60: bus=1,device=0,function=0,reg=0x00
Mar 09 09:28:11.233 CPU0: PCI: read request for device 'NM-1FE-TX(1)' at pc=0x60286c64: bus=1,device=0,function=0,reg=0x00
Mar 09 09:28:11.233 CPU0: PCI: write request (data=0x4d000000) for device 'NM-1FE-TX(1)' at pc=0x60286b2c: bus=1,device=0,function=0,reg=0x14
Mar 09 09:28:11.233 NM-1FE-TX(1): registers are mapped at 0x4d000000
Mar 09 09:28:11.233 CPU0: PCI: write request (data=0x4d000000) for device 'NM-1FE-TX(1)' at pc=0x60286b38: bus=1,device=0,function=0,reg=0x14
Mar 09 09:28:11.233 NM-1FE-TX(1): registers are mapped at 0x4d000000
Mar 09 09:28:11.233 CPU0: PCI: write request (data=0x00000006) for device 'NM-1FE-TX(1)' at pc=0x60286b2c: bus=1,device=0,function=0,reg=0x04
Mar 09 09:28:11.233 CPU0: PCI: write request (data=0x00000006) for device 'NM-1FE-TX(1)' at pc=0x60286b38: bus=1,device=0,function=0,reg=0x04
Mar 09 09:28:11.233 CPU0: PCI: write request (data=0x00004000) for device 'NM-1FE-TX(1)' at pc=0x60286b2c: bus=1,device=0,function=0,reg=0x0c
Mar 09 09:28:11.233 CPU0: PCI: write request (data=0x00004000) for device 'NM-1FE-TX(1)' at pc=0x60286b38: bus=1,device=0,function=0,reg=0x0c
Mar 09 09:28:11.233 CPU0: PCI: read request for device 'NM-1FE-TX(1)' at pc=0x60286c60: bus=1,device=0,function=0,reg=0x00
Mar 09 09:28:11.233 CPU0: PCI: read request for device 'NM-1FE-TX(1)' at pc=0x60286c64: bus=1,device=0,function=0,reg=0x00
Mar 09 09:28:11.234 CPU0: PCI: write request (data=0x00004000) for device 'NM-1FE-TX(1)' at pc=0x60286b2c: bus=1,device=0,function=0,reg=0x0c
Mar 09 09:28:11.234 CPU0: PCI: write request (data=0x00004000) for device 'NM-1FE-TX(1)' at pc=0x60286b38: bus=1,device=0,function=0,reg=0x0c
Mar 09 09:28:11.244 NM-1FE-TX(1): fetching init block at address 0x0f7e43a0
Mar 09 09:28:11.244 NM-1FE-TX(1): rx_ring = 0x0f7e4400 (64), tx_ring = 0x0f7e4840 (128)
Mar 09 09:28:11.244 NM-1FE-TX(1): CSR0 = 0x0101
Mar 09 09:28:11.296 CPU0: JIT: flushing data structures (compiled pages=277)
Mar 09 09:28:11.318 CPU0: IO_FPGA: read from unknown addr 0x4c, pc=0x60277d00 (size=2)
Mar 09 09:28:11.318 CPU0: IO_FPGA: write to unknown addr 0x4c, value=0x0, pc=0x60277d08 (size=2)
Mar 09 09:28:11.318 CPU0: IO_FPGA: read from unknown addr 0x2e, pc=0x60277d28 (size=2)
Mar 09 09:28:11.318 CPU0: IO_FPGA: write to unknown addr 0x2e, value=0x40, pc=0x60277d38 (size=2)
Mar 09 09:28:11.324 CPU0: MTS: read  access to undefined address 0x3c080001 at pc=0x6069ccb0 (size=1)
Mar 09 09:28:11.324 CPU0: MTS: write access to undefined address 0x3c080001 at pc=0x6069cce8, value=0x00000000 (size=1)
Mar 09 09:28:11.325 CPU0: MTS: read  access to undefined address 0x3c080025 at pc=0x60676ae0 (size=1)
Mar 09 09:28:11.325 CPU0: MTS: write access to undefined address 0x3c080025 at pc=0x60676aec, value=0x00000000 (size=1)
Mar 09 09:28:11.325 CPU0: MTS: read  access to undefined address 0x3c080026 at pc=0x60676e14 (size=1)
Mar 09 09:28:11.325 CPU0: MTS: write access to undefined address 0x3c080026 at pc=0x60676e20, value=0x00000000 (size=1)
Mar 09 09:28:11.326 CPU0: MTS: read  access to undefined address 0x3c08001f at pc=0x60677028 (size=1)
Mar 09 09:28:11.326 CPU0: MTS: write access to undefined address 0x3c08001f at pc=0x60676f78, value=0x00000010 (size=1)
Mar 09 09:28:11.327 CPU0: MTS: read  access to undefined address 0x3c080001 at pc=0x6069ce5c (size=1)
Mar 09 09:28:11.327 CPU0: MTS: write access to undefined address 0x3c080001 at pc=0x6069ce80, value=0x00000008 (size=1)
Mar 09 09:28:11.327 CPU0: MTS: read  access to undefined address 0x3c080004 at pc=0x6069cea0 (size=1)
Mar 09 09:28:11.327 CPU0: MTS: write access to undefined address 0x3c080004 at pc=0x6069cea8, value=0x00000002 (size=1)
Mar 09 09:28:11.327 CPU0: MTS: read  access to undefined address 0x3c080004 at pc=0x6069cebc (size=1)
Mar 09 09:28:11.327 CPU0: MTS: write access to undefined address 0x3c080004 at pc=0x6069cef8, value=0x00000000 (size=1)
Mar 09 09:28:11.329 CPU0: MTS: read  access to undefined address 0x3c080025 at pc=0x60676ae0 (size=1)
Mar 09 09:28:11.329 CPU0: MTS: write access to undefined address 0x3c080025 at pc=0x60676aec, value=0x00000000 (size=1)
Mar 09 09:28:11.330 CPU0: MTS: read  access to undefined address 0x3c080026 at pc=0x60676bf0 (size=1)
Mar 09 09:28:11.330 CPU0: MTS: write access to undefined address 0x3c080026 at pc=0x60676e20, value=0x00000002 (size=1)
Mar 09 09:28:11.330 CPU0: MTS: read  access to undefined address 0x3c08001f at pc=0x60676f6c (size=1)
Mar 09 09:28:11.330 CPU0: MTS: write access to undefined address 0x3c08001f at pc=0x60676f78, value=0x00000000 (size=1)
Mar 09 09:28:11.330 CPU0: MTS: read  access to undefined address 0x3c080001 at pc=0x6069cc18 (size=1)
Mar 09 09:28:11.330 CPU0: MTS: write access to undefined address 0x3c080001 at pc=0x6069cc20, value=0x00000000 (size=1)
Mar 09 09:28:11.330 CPU0: MTS: read  access to undefined address 0x3c080001 at pc=0x6069cc40 (size=1)
Mar 09 09:28:11.330 CPU0: MTS: write access to undefined address 0x3c080001 at pc=0x6069cc48, value=0x00000000 (size=1)
Mar 09 09:28:11.330 CPU0: MTS: read  access to undefined address 0x3c080001 at pc=0x6069cc5c (size=1)
Mar 09 09:28:11.330 CPU0: MTS: write access to undefined address 0x3c080001 at pc=0x6069cce8, value=0x00000004 (size=1)
Mar 09 09:28:11.330 CPU0: MTS: read  access to undefined address 0x3c08001f at pc=0x6067697c (size=1)
Mar 09 09:28:11.334 NM-1FE-TX(1): fetching init block at address 0x0f7e43a0
Mar 09 09:28:11.334 NM-1FE-TX(1): rx_ring = 0x0f7e4400 (64), tx_ring = 0x0f7e4840 (128)
Mar 09 09:28:11.334 NM-1FE-TX(1): CSR0 = 0x0101
Mar 09 09:28:11.369 CPU0: JIT: partial JIT flush (count=199)
Mar 09 09:28:11.428 CPU0: JIT: flushing data structures (compiled pages=281)
Mar 09 09:28:11.499 CPU0: JIT: partial JIT flush (count=200)
Mar 09 09:28:11.535 CPU0: MTS: read  access to undefined address 0x3c080001 at pc=0x6069ccb0 (size=1)
Mar 09 09:28:11.535 CPU0: MTS: write access to undefined address 0x3c080001 at pc=0x6069cce8, value=0x00000000 (size=1)
Mar 09 09:28:11.535 CPU0: MTS: read  access to undefined address 0x3c080025 at pc=0x60676ae0 (size=1)
Mar 09 09:28:11.535 CPU0: MTS: write access to undefined address 0x3c080025 at pc=0x60676aec, value=0x00000000 (size=1)
Mar 09 09:28:11.535 CPU0: MTS: read  access to undefined address 0x3c080026 at pc=0x60676e14 (size=1)
Mar 09 09:28:11.535 CPU0: MTS: write access to undefined address 0x3c080026 at pc=0x60676e20, value=0x00000000 (size=1)
Mar 09 09:28:11.536 CPU0: MTS: read  access to undefined address 0x3c08001f at pc=0x60677028 (size=1)
Mar 09 09:28:11.536 CPU0: MTS: write access to undefined address 0x3c08001f at pc=0x60676f78, value=0x00000010 (size=1)
Mar 09 09:28:11.538 CPU0: MTS: read  access to undefined address 0x3c080001 at pc=0x6069ce5c (size=1)
Mar 09 09:28:11.538 CPU0: MTS: write access to undefined address 0x3c080001 at pc=0x6069ce80, value=0x00000008 (size=1)
Mar 09 09:28:11.538 CPU0: MTS: read  access to undefined address 0x3c080004 at pc=0x6069cea0 (size=1)
Mar 09 09:28:11.538 CPU0: MTS: write access to undefined address 0x3c080004 at pc=0x6069cea8, value=0x00000002 (size=1)
Mar 09 09:28:11.538 CPU0: MTS: read  access to undefined address 0x3c080004 at pc=0x6069cebc (size=1)
Mar 09 09:28:11.538 CPU0: MTS: write access to undefined address 0x3c080004 at pc=0x6069cef8, value=0x00000000 (size=1)
Mar 09 09:28:11.540 CPU0: MTS: read  access to undefined address 0x3c080025 at pc=0x60676ae0 (size=1)
Mar 09 09:28:11.540 CPU0: MTS: write access to undefined address 0x3c080025 at pc=0x60676aec, value=0x00000000 (size=1)
Mar 09 09:28:11.540 CPU0: MTS: read  access to undefined address 0x3c080026 at pc=0x60676bf0 (size=1)
Mar 09 09:28:11.540 CPU0: MTS: write access to undefined address 0x3c080026 at pc=0x60676e20, value=0x00000002 (size=1)
Mar 09 09:28:11.540 CPU0: MTS: read  access to undefined address 0x3c08001f at pc=0x60676f6c (size=1)
Mar 09 09:28:11.540 CPU0: MTS: write access to undefined address 0x3c08001f at pc=0x60676f78, value=0x00000000 (size=1)
Mar 09 09:28:11.540 CPU0: MTS: read  access to undefined address 0x3c080001 at pc=0x6069cc18 (size=1)
Mar 09 09:28:11.540 CPU0: MTS: write access to undefined address 0x3c080001 at pc=0x6069cc20, value=0x00000000 (size=1)
Mar 09 09:28:11.540 CPU0: MTS: read  access to undefined address 0x3c080001 at pc=0x6069cc40 (size=1)
Mar 09 09:28:11.540 CPU0: MTS: write access to undefined address 0x3c080001 at pc=0x6069cc48, value=0x00000000 (size=1)
Mar 09 09:28:11.540 CPU0: MTS: read  access to undefined address 0x3c080001 at pc=0x6069cc5c (size=1)
Mar 09 09:28:11.540 CPU0: MTS: write access to undefined address 0x3c080001 at pc=0x6069cce8, value=0x00000004 (size=1)
Mar 09 09:28:11.540 CPU0: MTS: read  access to undefined address 0x3c08001f at pc=0x6067697c (size=1)
Mar 09 09:28:11.544 NM-1FE-TX(1): fetching init block at address 0x0f7e43a0
Mar 09 09:28:11.544 NM-1FE-TX(1): rx_ring = 0x0f7e4400 (64), tx_ring = 0x0f7e4840 (128)
Mar 09 09:28:11.544 NM-1FE-TX(1): CSR0 = 0x0101
Mar 09 09:28:11.563 CPU0: MTS: read  access to undefined address 0x3c080001 at pc=0x6069ccb0 (size=1)
Mar 09 09:28:11.564 CPU0: MTS: write access to undefined address 0x3c080001 at pc=0x6069cce8, value=0x00000000 (size=1)
Mar 09 09:28:11.564 CPU0: MTS: read  access to undefined address 0x3c080025 at pc=0x60676ae0 (size=1)
Mar 09 09:28:11.564 CPU0: MTS: write access to undefined address 0x3c080025 at pc=0x60676aec, value=0x00000000 (size=1)
Mar 09 09:28:11.564 CPU0: MTS: read  access to undefined address 0x3c080026 at pc=0x60676e14 (size=1)
Mar 09 09:28:11.564 CPU0: MTS: write access to undefined address 0x3c080026 at pc=0x60676e20, value=0x00000000 (size=1)
Mar 09 09:28:11.564 CPU0: MTS: read  access to undefined address 0x3c08001f at pc=0x60677028 (size=1)
Mar 09 09:28:11.564 CPU0: MTS: write access to undefined address 0x3c08001f at pc=0x60676f78, value=0x00000010 (size=1)
Mar 09 09:28:11.564 CPU0: MTS: read  access to undefined address 0x3c080001 at pc=0x6069ce5c (size=1)
Mar 09 09:28:11.564 CPU0: MTS: write access to undefined address 0x3c080001 at pc=0x6069ce80, value=0x00000008 (size=1)
Mar 09 09:28:11.564 CPU0: MTS: read  access to undefined address 0x3c080004 at pc=0x6069cea0 (size=1)
Mar 09 09:28:11.564 CPU0: MTS: write access to undefined address 0x3c080004 at pc=0x6069cea8, value=0x00000002 (size=1)
Mar 09 09:28:11.564 CPU0: MTS: read  access to undefined address 0x3c080004 at pc=0x6069cebc (size=1)
Mar 09 09:28:11.564 CPU0: MTS: write access to undefined address 0x3c080004 at pc=0x6069cef8, value=0x00000000 (size=1)
Mar 09 09:28:11.564 CPU0: MTS: read  access to undefined address 0x3c080025 at pc=0x60676ae0 (size=1)
Mar 09 09:28:11.564 CPU0: MTS: write access to undefined address 0x3c080025 at pc=0x60676aec, value=0x00000000 (size=1)
Mar 09 09:28:11.564 CPU0: MTS: read  access to undefined address 0x3c080026 at pc=0x60676bf0 (size=1)
Mar 09 09:28:11.564 CPU0: MTS: write access to undefined address 0x3c080026 at pc=0x60676e20, value=0x00000002 (size=1)
Mar 09 09:28:11.564 CPU0: MTS: read  access to undefined address 0x3c08001f at pc=0x60676f6c (size=1)
Mar 09 09:28:11.564 CPU0: MTS: write access to undefined address 0x3c08001f at pc=0x60676f78, value=0x00000000 (size=1)
Mar 09 09:28:11.564 CPU0: MTS: read  access to undefined address 0x3c080001 at pc=0x6069cc18 (size=1)
Mar 09 09:28:11.564 CPU0: MTS: write access to undefined address 0x3c080001 at pc=0x6069cc20, value=0x00000000 (size=1)
Mar 09 09:28:11.564 CPU0: MTS: read  access to undefined address 0x3c080001 at pc=0x6069cc40 (size=1)
Mar 09 09:28:11.564 CPU0: MTS: write access to undefined address 0x3c080001 at pc=0x6069cc48, value=0x00000000 (size=1)
Mar 09 09:28:11.564 CPU0: MTS: read  access to undefined address 0x3c080001 at pc=0x6069cc5c (size=1)
Mar 09 09:28:11.564 CPU0: MTS: write access to undefined address 0x3c080001 at pc=0x6069cce8, value=0x00000004 (size=1)
Mar 09 09:28:11.564 CPU0: MTS: read  access to undefined address 0x3c08001f at pc=0x6067697c (size=1)
Mar 09 09:28:11.566 NM-1FE-TX(1): fetching init block at address 0x0f7e43a0
Mar 09 09:28:11.566 NM-1FE-TX(1): rx_ring = 0x0f7e4400 (64), tx_ring = 0x0f7e4840 (128)
Mar 09 09:28:11.566 NM-1FE-TX(1): CSR0 = 0x0101
Mar 09 09:28:11.569 CPU0: MTS: read  access to undefined address 0x3c080001 at pc=0x6069ccb0 (size=1)
Mar 09 09:28:11.569 CPU0: MTS: write access to undefined address 0x3c080001 at pc=0x6069cce8, value=0x00000000 (size=1)
Mar 09 09:28:11.569 CPU0: MTS: read  access to undefined address 0x3c080025 at pc=0x60676ae0 (size=1)
Mar 09 09:28:11.569 CPU0: MTS: write access to undefined address 0x3c080025 at pc=0x60676aec, value=0x00000000 (size=1)
Mar 09 09:28:11.569 CPU0: MTS: read  access to undefined address 0x3c080026 at pc=0x60676e14 (size=1)
Mar 09 09:28:11.569 CPU0: MTS: write access to undefined address 0x3c080026 at pc=0x60676e20, value=0x00000000 (size=1)
Mar 09 09:28:11.569 CPU0: MTS: read  access to undefined address 0x3c08001f at pc=0x60677028 (size=1)
Mar 09 09:28:11.569 CPU0: MTS: write access to undefined address 0x3c08001f at pc=0x60676f78, value=0x00000010 (size=1)
Mar 09 09:28:11.569 CPU0: MTS: read  access to undefined address 0x3c080001 at pc=0x6069ce5c (size=1)
Mar 09 09:28:11.569 CPU0: MTS: write access to undefined address 0x3c080001 at pc=0x6069ce80, value=0x00000008 (size=1)
Mar 09 09:28:11.569 CPU0: MTS: read  access to undefined address 0x3c080004 at pc=0x6069cea0 (size=1)
Mar 09 09:28:11.569 CPU0: MTS: write access to undefined address 0x3c080004 at pc=0x6069cea8, value=0x00000002 (size=1)
Mar 09 09:28:11.569 CPU0: MTS: read  access to undefined address 0x3c080004 at pc=0x6069cebc (size=1)
Mar 09 09:28:11.569 CPU0: MTS: write access to undefined address 0x3c080004 at pc=0x6069cef8, value=0x00000000 (size=1)
Mar 09 09:28:11.569 CPU0: MTS: read  access to undefined address 0x3c080025 at pc=0x60676ae0 (size=1)
Mar 09 09:28:11.569 CPU0: MTS: write access to undefined address 0x3c080025 at pc=0x60676aec, value=0x00000000 (size=1)
Mar 09 09:28:11.569 CPU0: MTS: read  access to undefined address 0x3c080026 at pc=0x60676bf0 (size=1)
Mar 09 09:28:11.569 CPU0: MTS: write access to undefined address 0x3c080026 at pc=0x60676e20, value=0x00000002 (size=1)
Mar 09 09:28:11.569 CPU0: MTS: read  access to undefined address 0x3c08001f at pc=0x60676f6c (size=1)
Mar 09 09:28:11.569 CPU0: MTS: write access to undefined address 0x3c08001f at pc=0x60676f78, value=0x00000000 (size=1)
Mar 09 09:28:11.569 CPU0: MTS: read  access to undefined address 0x3c080001 at pc=0x6069cc18 (size=1)
Mar 09 09:28:11.569 CPU0: MTS: write access to undefined address 0x3c080001 at pc=0x6069cc20, value=0x00000000 (size=1)
Mar 09 09:28:11.569 CPU0: MTS: read  access to undefined address 0x3c080001 at pc=0x6069cc40 (size=1)
Mar 09 09:28:11.569 CPU0: MTS: write access to undefined address 0x3c080001 at pc=0x6069cc48, value=0x00000000 (size=1)
Mar 09 09:28:11.569 CPU0: MTS: read  access to undefined address 0x3c080001 at pc=0x6069cc5c (size=1)
Mar 09 09:28:11.569 CPU0: MTS: write access to undefined address 0x3c080001 at pc=0x6069cce8, value=0x00000004 (size=1)
Mar 09 09:28:11.569 CPU0: MTS: read  access to undefined address 0x3c08001f at pc=0x6067697c (size=1)
Mar 09 09:28:11.571 NM-1FE-TX(1): fetching init block at address 0x0f7e43a0
Mar 09 09:28:11.571 NM-1FE-TX(1): rx_ring = 0x0f7e4400 (64), tx_ring = 0x0f7e4840 (128)
Mar 09 09:28:11.571 NM-1FE-TX(1): CSR0 = 0x0101
Mar 09 09:28:11.575 CPU0: JIT: flushing data structures (compiled pages=308)
Mar 09 09:28:11.698 CPU0: JIT: partial JIT flush (count=201)
Mar 09 09:28:11.753 CPU0: MTS: read  access to undefined address 0x3c080001 at pc=0x6069ccb0 (size=1)
Mar 09 09:28:11.753 CPU0: MTS: write access to undefined address 0x3c080001 at pc=0x6069cce8, value=0x00000000 (size=1)
Mar 09 09:28:11.753 CPU0: MTS: read  access to undefined address 0x3c080025 at pc=0x60676ae0 (size=1)
Mar 09 09:28:11.753 CPU0: MTS: write access to undefined address 0x3c080025 at pc=0x60676aec, value=0x00000000 (size=1)
Mar 09 09:28:11.753 CPU0: MTS: read  access to undefined address 0x3c080026 at pc=0x60676e14 (size=1)
Mar 09 09:28:11.753 CPU0: MTS: write access to undefined address 0x3c080026 at pc=0x60676e20, value=0x00000000 (size=1)
Mar 09 09:28:11.754 CPU0: MTS: read  access to undefined address 0x3c08001f at pc=0x60677028 (size=1)
Mar 09 09:28:11.754 CPU0: MTS: write access to undefined address 0x3c08001f at pc=0x60676f78, value=0x00000010 (size=1)
Mar 09 09:28:11.756 CPU0: MTS: read  access to undefined address 0x3c080001 at pc=0x6069ce5c (size=1)
Mar 09 09:28:11.756 CPU0: MTS: write access to undefined address 0x3c080001 at pc=0x6069ce80, value=0x00000008 (size=1)
Mar 09 09:28:11.756 CPU0: MTS: read  access to undefined address 0x3c080004 at pc=0x6069cea0 (size=1)
Mar 09 09:28:11.756 CPU0: MTS: write access to undefined address 0x3c080004 at pc=0x6069cea8, value=0x00000002 (size=1)
Mar 09 09:28:11.756 CPU0: MTS: read  access to undefined address 0x3c080004 at pc=0x6069cebc (size=1)
Mar 09 09:28:11.756 CPU0: MTS: write access to undefined address 0x3c080004 at pc=0x6069cef8, value=0x00000000 (size=1)
Mar 09 09:28:11.758 CPU0: MTS: read  access to undefined address 0x3c080025 at pc=0x60676ae0 (size=1)
Mar 09 09:28:11.758 CPU0: MTS: write access to undefined address 0x3c080025 at pc=0x60676aec, value=0x00000000 (size=1)
Mar 09 09:28:11.758 CPU0: MTS: read  access to undefined address 0x3c080026 at pc=0x60676bf0 (size=1)
Mar 09 09:28:11.758 CPU0: MTS: write access to undefined address 0x3c080026 at pc=0x60676e20, value=0x00000002 (size=1)
Mar 09 09:28:11.758 CPU0: MTS: read  access to undefined address 0x3c08001f at pc=0x60676f6c (size=1)
Mar 09 09:28:11.758 CPU0: MTS: write access to undefined address 0x3c08001f at pc=0x60676f78, value=0x00000000 (size=1)
Mar 09 09:28:11.758 CPU0: MTS: read  access to undefined address 0x3c080001 at pc=0x6069cc18 (size=1)
Mar 09 09:28:11.758 CPU0: MTS: write access to undefined address 0x3c080001 at pc=0x6069cc20, value=0x00000000 (size=1)
Mar 09 09:28:11.758 CPU0: MTS: read  access to undefined address 0x3c080001 at pc=0x6069cc40 (size=1)
Mar 09 09:28:11.758 CPU0: MTS: write access to undefined address 0x3c080001 at pc=0x6069cc48, value=0x00000000 (size=1)
Mar 09 09:28:11.758 CPU0: MTS: read  access to undefined address 0x3c080001 at pc=0x6069cc5c (size=1)
Mar 09 09:28:11.758 CPU0: MTS: write access to undefined address 0x3c080001 at pc=0x6069cce8, value=0x00000004 (size=1)
Mar 09 09:28:11.758 CPU0: MTS: read  access to undefined address 0x3c08001f at pc=0x6067697c (size=1)
Mar 09 09:28:11.762 NM-1FE-TX(1): fetching init block at address 0x0f7e43a0
Mar 09 09:28:11.762 NM-1FE-TX(1): rx_ring = 0x0f7e4400 (64), tx_ring = 0x0f7e4840 (128)
Mar 09 09:28:11.762 NM-1FE-TX(1): CSR0 = 0x0101
Mar 09 09:28:11.776 CPU0: JIT: flushing data structures (compiled pages=311)
Mar 09 09:28:12.088 CPU0: JIT: partial JIT flush (count=165)
Mar 09 09:28:12.140 CPU0: JIT: flushing data structures (compiled pages=308)
Mar 09 09:28:12.228 CPU0: JIT: partial JIT flush (count=199)
Mar 09 09:28:12.320 CPU0: JIT: flushing data structures (compiled pages=310)
Mar 09 09:28:12.403 CPU0: JIT: partial JIT flush (count=202)
Mar 09 09:28:12.557 CPU0: JIT: flushing data structures (compiled pages=318)
Mar 09 09:28:12.630 CPU0: JIT: partial JIT flush (count=199)
Mar 09 09:28:12.703 CPU0: JIT: flushing data structures (compiled pages=318)
Mar 09 09:28:12.779 CPU0: JIT: partial JIT flush (count=189)
Mar 09 09:28:12.895 CPU0: JIT: flushing data structures (compiled pages=327)
Mar 09 09:28:13.016 CPU0: JIT: partial JIT flush (count=165)
Mar 09 09:28:13.268 CPU0: JIT: flushing data structures (compiled pages=559)
Mar 09 09:28:13.342 CPU0: JIT: partial JIT flush (count=189)
Mar 09 09:28:13.895 CPU0: JIT: flushing data structures (compiled pages=555)
Mar 09 09:28:13.936 ROM: trying to read bootvar 'PMDEBUG'
Mar 09 09:28:13.949 ROM: trying to read bootvar 'MONDEBUG'
Mar 09 09:28:14.040 CPU0: JIT: partial JIT flush (count=199)
Mar 09 09:28:14.430 CPU0: JIT: flushing data structures (compiled pages=562)
Mar 09 09:28:14.665 CPU0: JIT: partial JIT flush (count=193)
Mar 09 09:28:14.815 CPU0: JIT: flushing data structures (compiled pages=562)
Mar 09 09:28:14.865 CPU0: JIT: partial JIT flush (count=213)
Mar 09 09:28:14.898 ROM: unhandled syscall 0x0000001a at pc=0x60a9e9bc (a1=0x65024a6c,a2=0x00000001,a3=0x00000023)
Mar 09 09:28:14.898 ROM: unhandled syscall 0x00000009 at pc=0x60a9e9bc (a1=0x65024a6c,a2=0x00000001,a3=0x00000023)
Mar 09 09:28:14.943 CPU0: JIT: flushing data structures (compiled pages=557)
Mar 09 09:28:15.038 CPU0: JIT: partial JIT flush (count=194)
Mar 09 09:28:15.119 CPU0: JIT: flushing data structures (compiled pages=564)
Mar 09 09:28:15.173 CPU0: JIT: partial JIT flush (count=215)
Mar 09 09:28:15.235 CPU0: JIT: flushing data structures (compiled pages=552)
Mar 09 09:28:15.299 CPU0: JIT: partial JIT flush (count=213)
Mar 09 09:28:15.398 CPU0: JIT: flushing data structures (compiled pages=557)
Mar 09 09:28:15.635 CPU0: JIT: partial JIT flush (count=181)
Mar 09 09:28:15.713 CPU0: JIT: flushing data structures (compiled pages=558)
Mar 09 09:28:15.849 CPU0: JIT: partial JIT flush (count=182)
Mar 09 09:28:15.899 CPU0: JIT: flushing data structures (compiled pages=555)
Mar 09 09:28:15.982 CPU0: JIT: partial JIT flush (count=209)
Mar 09 09:28:16.032 CPU0: JIT: flushing data structures (compiled pages=554)
Mar 09 09:28:16.102 CPU0: JIT: partial JIT flush (count=207)
Mar 09 09:28:16.171 CPU0: JIT: flushing data structures (compiled pages=558)
Mar 09 09:28:16.284 CPU0: JIT: partial JIT flush (count=206)
Mar 09 09:28:16.343 CPU0: JIT: flushing data structures (compiled pages=559)
Mar 09 09:28:16.406 CPU0: MTS: read  access to undefined address 0x3c080001 at pc=0x6069ccb0 (size=1)
Mar 09 09:28:16.406 CPU0: MTS: write access to undefined address 0x3c080001 at pc=0x6069cce8, value=0x00000000 (size=1)
Mar 09 09:28:16.406 CPU0: MTS: read  access to undefined address 0x3c080025 at pc=0x60676ae0 (size=1)
Mar 09 09:28:16.406 CPU0: MTS: write access to undefined address 0x3c080025 at pc=0x60676aec, value=0x00000000 (size=1)
Mar 09 09:28:16.406 CPU0: MTS: read  access to undefined address 0x3c080026 at pc=0x60676e14 (size=1)
Mar 09 09:28:16.406 CPU0: MTS: write access to undefined address 0x3c080026 at pc=0x60676e20, value=0x00000000 (size=1)
Mar 09 09:28:16.407 CPU0: MTS: read  access to undefined address 0x3c08001f at pc=0x60677028 (size=1)
Mar 09 09:28:16.407 CPU0: MTS: write access to undefined address 0x3c08001f at pc=0x60676f78, value=0x00000010 (size=1)
Mar 09 09:28:16.409 CPU0: JIT: partial JIT flush (count=207)
Mar 09 09:28:16.419 CPU0: MTS: read  access to undefined address 0x3c080001 at pc=0x6069ce5c (size=1)
Mar 09 09:28:16.419 CPU0: MTS: write access to undefined address 0x3c080001 at pc=0x6069ce80, value=0x00000008 (size=1)
Mar 09 09:28:16.419 CPU0: MTS: read  access to undefined address 0x3c080004 at pc=0x6069cea0 (size=1)
Mar 09 09:28:16.419 CPU0: MTS: write access to undefined address 0x3c080004 at pc=0x6069cea8, value=0x00000002 (size=1)
Mar 09 09:28:16.419 CPU0: MTS: read  access to undefined address 0x3c080004 at pc=0x6069cebc (size=1)
Mar 09 09:28:16.419 CPU0: MTS: write access to undefined address 0x3c080004 at pc=0x6069cef8, value=0x00000000 (size=1)
Mar 09 09:28:16.422 CPU0: MTS: read  access to undefined address 0x3c080025 at pc=0x60676ae0 (size=1)
Mar 09 09:28:16.422 CPU0: MTS: write access to undefined address 0x3c080025 at pc=0x60676aec, value=0x00000000 (size=1)
Mar 09 09:28:16.422 CPU0: MTS: read  access to undefined address 0x3c080026 at pc=0x60676bf0 (size=1)
Mar 09 09:28:16.422 CPU0: MTS: write access to undefined address 0x3c080026 at pc=0x60676e20, value=0x00000002 (size=1)
Mar 09 09:28:16.422 CPU0: MTS: read  access to undefined address 0x3c08001f at pc=0x60676f6c (size=1)
Mar 09 09:28:16.422 CPU0: MTS: write access to undefined address 0x3c08001f at pc=0x60676f78, value=0x00000000 (size=1)
Mar 09 09:28:16.422 CPU0: MTS: read  access to undefined address 0x3c080001 at pc=0x6069cc18 (size=1)
Mar 09 09:28:16.422 CPU0: MTS: write access to undefined address 0x3c080001 at pc=0x6069cc20, value=0x00000000 (size=1)
Mar 09 09:28:16.422 CPU0: MTS: read  access to undefined address 0x3c080001 at pc=0x6069cc40 (size=1)
Mar 09 09:28:16.422 CPU0: MTS: write access to undefined address 0x3c080001 at pc=0x6069cc48, value=0x00000000 (size=1)
Mar 09 09:28:16.422 CPU0: MTS: read  access to undefined address 0x3c080001 at pc=0x6069cc5c (size=1)
Mar 09 09:28:16.422 CPU0: MTS: write access to undefined address 0x3c080001 at pc=0x6069cce8, value=0x00000004 (size=1)
Mar 09 09:28:16.422 CPU0: MTS: read  access to undefined address 0x3c08001f at pc=0x6067697c (size=1)
Mar 09 09:28:16.465 CPU0: JIT: flushing data structures (compiled pages=557)
Mar 09 09:28:16.541 CPU0: JIT: partial JIT flush (count=207)
Mar 09 09:28:16.569 CPU0: MTS: read  access to undefined address 0x3c080001 at pc=0x6069ccb0 (size=1)
Mar 09 09:28:16.569 CPU0: MTS: write access to undefined address 0x3c080001 at pc=0x6069cce8, value=0x00000000 (size=1)
Mar 09 09:28:16.570 CPU0: MTS: read  access to undefined address 0x3c080025 at pc=0x60676ae0 (size=1)
Mar 09 09:28:16.570 CPU0: MTS: write access to undefined address 0x3c080025 at pc=0x60676aec, value=0x00000000 (size=1)
Mar 09 09:28:16.570 CPU0: MTS: read  access to undefined address 0x3c080026 at pc=0x60676e14 (size=1)
Mar 09 09:28:16.570 CPU0: MTS: write access to undefined address 0x3c080026 at pc=0x60676e20, value=0x00000000 (size=1)
Mar 09 09:28:16.571 CPU0: MTS: read  access to undefined address 0x3c08001f at pc=0x60677028 (size=1)
Mar 09 09:28:16.571 CPU0: MTS: write access to undefined address 0x3c08001f at pc=0x60676f78, value=0x00000010 (size=1)
Mar 09 09:28:16.591 CPU0: JIT: flushing data structures (compiled pages=557)
Mar 09 09:28:16.661 CPU0: JIT: partial JIT flush (count=203)
Mar 09 09:28:16.710 CPU0: JIT: flushing data structures (compiled pages=565)
Mar 09 09:28:16.769 CPU0: JIT: partial JIT flush (count=211)
Mar 09 09:28:16.829 CPU0: JIT: flushing data structures (compiled pages=563)
Mar 09 09:28:16.834 NM-1FE-TX(1): fetching init block at address 0x0f7e43a0
Mar 09 09:28:16.834 NM-1FE-TX(1): rx_ring = 0x0f7e4400 (64), tx_ring = 0x0f7e4840 (128)
Mar 09 09:28:16.834 NM-1FE-TX(1): CSR0 = 0x0101
Mar 09 09:28:16.900 CPU0: JIT: partial JIT flush (count=210)
Mar 09 09:28:16.974 CPU0: JIT: flushing data structures (compiled pages=560)
Mar 09 09:28:17.057 CPU0: JIT: partial JIT flush (count=206)
Mar 09 09:28:17.100 ROM: trying to read bootvar 'RANDOM_NUM'
Mar 09 09:28:17.111 CPU0: JIT: flushing data structures (compiled pages=565)
Mar 09 09:28:17.372 CPU0: JIT: partial JIT flush (count=186)
Mar 09 09:28:17.382 CPU0: IO_FPGA: read from unknown addr 0x16, pc=0x608192f4 (size=2)
Mar 09 09:28:17.383 CPU0: IO_FPGA: write to unknown addr 0x16, value=0x1, pc=0x608192fc (size=2)
Mar 09 09:28:17.394 ROM: trying to read bootvar 'ROM_PERSISTENT_UTC'
Mar 09 09:28:17.498 CPU0: JIT: flushing data structures (compiled pages=572)
Mar 09 09:28:17.567 CPU0: JIT: partial JIT flush (count=197)
Mar 09 09:28:17.626 CPU0: JIT: flushing data structures (compiled pages=564)
Mar 09 09:28:17.686 CPU0: JIT: partial JIT flush (count=216)
Mar 09 09:28:17.753 CPU0: JIT: flushing data structures (compiled pages=563)
Mar 09 09:28:17.811 CPU0: JIT: partial JIT flush (count=215)
Mar 09 09:28:17.876 CPU0: MTS: read  access to undefined address 0x3c08002c at pc=0x60819f48 (size=1)
Mar 09 09:28:18.011 CPU0: JIT: flushing data structures (compiled pages=563)
Mar 09 09:28:18.067 CPU0: JIT: partial JIT flush (count=204)
Mar 09 09:28:18.226 CPU0: MTS: read  access to undefined address 0x3c08002c at pc=0x60819f48 (size=1)
Mar 09 09:28:18.229 CPU0: JIT: flushing data structures (compiled pages=568)
Mar 09 09:28:18.349 CPU0: JIT: partial JIT flush (count=204)
Mar 09 09:28:18.434 CPU0: JIT: flushing data structures (compiled pages=569)
Mar 09 09:28:18.491 CPU0: JIT: partial JIT flush (count=197)
Mar 09 09:28:18.510 ROM: trying to set bootvar 'BSI=0'
Mar 09 09:28:18.540 ROM: trying to read bootvar 'RET_2_RCALTS'
Mar 09 09:28:18.540 ROM: trying to set bootvar 'RET_2_RCALTS='
Mar 09 09:28:18.608 CPU0: JIT: flushing data structures (compiled pages=572)
Mar 09 09:28:18.609 CPU0: MTS: read  access to undefined address 0x3c08002c at pc=0x60819f48 (size=1)
Mar 09 09:28:18.663 CPU0: JIT: partial JIT flush (count=211)
Mar 09 09:28:18.714 CPU0: JIT: flushing data structures (compiled pages=564)
Mar 09 09:28:18.811 CPU0: JIT: partial JIT flush (count=200)
Mar 09 09:28:18.863 CPU0: MTS: read  access to undefined address 0x3c08002c at pc=0x60819f48 (size=1)
Mar 09 09:28:18.877 CPU0: JIT: flushing data structures (compiled pages=568)
Mar 09 09:28:18.947 CPU0: JIT: partial JIT flush (count=199)
Mar 09 09:28:19.007 CPU0: MTS: read  access to undefined address 0x3c08002c at pc=0x60819f48 (size=1)
Mar 09 09:28:19.015 CPU0: JIT: flushing data structures (compiled pages=569)
Mar 09 09:28:19.070 CPU0: JIT: partial JIT flush (count=206)
Mar 09 09:28:19.152 CPU0: JIT: flushing data structures (compiled pages=561)
Mar 09 09:28:19.218 CPU0: MTS: read  access to undefined address 0x3c08002c at pc=0x60819f48 (size=1)
Mar 09 09:28:19.442 CPU0: JIT: partial JIT flush (count=175)
Mar 09 09:28:19.474 CPU0: MTS: read  access to undefined address 0x3c08002c at pc=0x60819f48 (size=1)
Mar 09 09:28:19.619 CPU0: JIT: flushing data structures (compiled pages=566)
Mar 09 09:28:19.712 CPU0: MTS: read  access to undefined address 0x3c08002c at pc=0x60819f48 (size=1)
Mar 09 09:28:19.815 CPU0: JIT: partial JIT flush (count=186)
Mar 09 09:28:19.962 CPU0: MTS: read  access to undefined address 0x3c08002c at pc=0x60819f48 (size=1)
Mar 09 09:28:20.027 CPU0: JIT: flushing data structures (compiled pages=571)
Mar 09 09:28:20.244 CPU0: MTS: read  access to undefined address 0x3c08002c at pc=0x60819f48 (size=1)
Mar 09 09:28:20.463 CPU0: MTS: read  access to undefined address 0x3c08002c at pc=0x60819f48 (size=1)
Mar 09 09:28:20.562 CPU0: JIT: partial JIT flush (count=167)
Mar 09 09:28:20.700 CPU0: MTS: read  access to undefined address 0x3c08002c at pc=0x60819f48 (size=1)
Mar 09 09:28:20.987 CPU0: MTS: read  access to undefined address 0x3c08002c at pc=0x60819f48 (size=1)
Mar 09 09:28:21.214 CPU0: MTS: read  access to undefined address 0x3c08002c at pc=0x60819f48 (size=1)
Mar 09 09:28:21.445 CPU0: JIT: flushing data structures (compiled pages=574)
Mar 09 09:28:21.492 CPU0: MTS: read  access to undefined address 0x3c08002c at pc=0x60819f48 (size=1)
Mar 09 09:28:21.719 CPU0: MTS: read  access to undefined address 0x3c08002c at pc=0x60819f48 (size=1)
Mar 09 09:28:21.969 CPU0: MTS: read  access to undefined address 0x3c08002c at pc=0x60819f48 (size=1)
Mar 09 09:28:22.219 CPU0: MTS: read  access to undefined address 0x3c08002c at pc=0x60819f48 (size=1)
Mar 09 09:28:22.469 CPU0: MTS: read  access to undefined address 0x3c08002c at pc=0x60819f48 (size=1)
Mar 09 09:28:22.726 CPU0: MTS: read  access to undefined address 0x3c08002c at pc=0x60819f48 (size=1)
Mar 09 09:28:22.976 CPU0: MTS: read  access to undefined address 0x3c08002c at pc=0x60819f48 (size=1)
Mar 09 09:28:23.226 CPU0: MTS: read  access to undefined address 0x3c08002c at pc=0x60819f48 (size=1)
Mar 09 09:28:23.476 CPU0: MTS: read  access to undefined address 0x3c08002c at pc=0x60819f48 (size=1)
Mar 09 09:28:23.719 CPU0: MTS: read  access to undefined address 0x3c08002c at pc=0x60819f48 (size=1)
Mar 09 09:28:23.970 CPU0: MTS: read  access to undefined address 0x3c08002c at pc=0x60819f48 (size=1)
Mar 09 09:28:24.220 CPU0: MTS: read  access to undefined address 0x3c08002c at pc=0x60819f48 (size=1)
Mar 09 09:28:24.470 CPU0: MTS: read  access to undefined address 0x3c08002c at pc=0x60819f48 (size=1)
Mar 09 09:28:24.715 CPU0: MTS: read  access to undefined address 0x3c08002c at pc=0x60819f48 (size=1)
Mar 09 09:28:24.965 CPU0: MTS: read  access to undefined address 0x3c08002c at pc=0x60819f48 (size=1)
Mar 09 09:28:25.215 CPU0: MTS: read  access to undefined address 0x3c08002c at pc=0x60819f48 (size=1)
Mar 09 09:28:25.262 CPU0: JIT: partial JIT flush (count=181)
Mar 09 09:28:25.452 CPU0: MTS: read  access to undefined address 0x3c08002c at pc=0x60819f48 (size=1)
Mar 09 09:28:25.727 CPU0: MTS: read  access to undefined address 0x3c08002c at pc=0x60819f48 (size=1)
Mar 09 09:28:25.977 CPU0: MTS: read  access to undefined address 0x3c08002c at pc=0x60819f48 (size=1)
Mar 09 09:28:26.227 CPU0: MTS: read  access to undefined address 0x3c08002c at pc=0x60819f48 (size=1)
Mar 09 09:28:26.477 CPU0: MTS: read  access to undefined address 0x3c08002c at pc=0x60819f48 (size=1)
Mar 09 09:28:26.727 CPU0: MTS: read  access to undefined address 0x3c08002c at pc=0x60819f48 (size=1)
Mar 09 09:28:26.977 CPU0: MTS: read  access to undefined address 0x3c08002c at pc=0x60819f48 (size=1)
Mar 09 09:28:27.227 CPU0: MTS: read  access to undefined address 0x3c08002c at pc=0x60819f48 (size=1)
Mar 09 09:28:27.477 CPU0: MTS: read  access to undefined address 0x3c08002c at pc=0x60819f48 (size=1)
Mar 09 09:28:27.704 CPU0: MTS: read  access to undefined address 0x3c08002c at pc=0x60819f48 (size=1)
Mar 09 09:28:27.954 CPU0: MTS: read  access to undefined address 0x3c08002c at pc=0x60819f48 (size=1)
Mar 09 09:28:28.204 CPU0: MTS: read  access to undefined address 0x3c08002c at pc=0x60819f48 (size=1)
Mar 09 09:28:28.454 CPU0: MTS: read  access to undefined address 0x3c08002c at pc=0x60819f48 (size=1)
Mar 09 09:28:28.548 CPU0: JIT: flushing data structures (compiled pages=569)
Mar 09 09:28:28.714 CPU0: MTS: read  access to undefined address 0x3c08002c at pc=0x60819f48 (size=1)
Mar 09 09:28:28.980 CPU0: MTS: read  access to undefined address 0x3c08002c at pc=0x60819f48 (size=1)
Mar 09 09:28:29.199 CPU0: MTS: read  access to undefined address 0x3c08002c at pc=0x60819f48 (size=1)
Mar 09 09:28:29.449 CPU0: JIT: partial JIT flush (count=200)
Mar 09 09:28:29.480 CPU0: MTS: read  access to undefined address 0x3c08002c at pc=0x60819f48 (size=1)
Mar 09 09:28:29.706 CPU0: MTS: read  access to undefined address 0x3c08002c at pc=0x60819f48 (size=1)
Mar 09 09:28:29.956 CPU0: MTS: read  access to undefined address 0x3c08002c at pc=0x60819f48 (size=1)
Mar 09 09:28:30.222 CPU0: MTS: read  access to undefined address 0x3c08002c at pc=0x60819f48 (size=1)
Mar 09 09:28:30.480 CPU0: MTS: read  access to undefined address 0x3c08002c at pc=0x60819f48 (size=1)
Mar 09 09:28:30.705 CPU0: MTS: read  access to undefined address 0x3c08002c at pc=0x60819f48 (size=1)
Mar 09 09:28:30.955 CPU0: MTS: read  access to undefined address 0x3c08002c at pc=0x60819f48 (size=1)
Mar 09 09:28:31.205 CPU0: MTS: read  access to undefined address 0x3c08002c at pc=0x60819f48 (size=1)
Mar 09 09:28:31.455 CPU0: MTS: read  access to undefined address 0x3c08002c at pc=0x60819f48 (size=1)
Mar 09 09:28:31.713 CPU0: MTS: read  access to undefined address 0x3c08002c at pc=0x60819f48 (size=1)
Mar 09 09:28:31.963 CPU0: MTS: read  access to undefined address 0x3c08002c at pc=0x60819f48 (size=1)
Mar 09 09:28:32.213 CPU0: MTS: read  access to undefined address 0x3c08002c at pc=0x60819f48 (size=1)
Mar 09 09:28:32.463 CPU0: MTS: read  access to undefined address 0x3c08002c at pc=0x60819f48 (size=1)
Mar 09 09:28:32.714 CPU0: MTS: read  access to undefined address 0x3c08002c at pc=0x60819f48 (size=1)
Mar 09 09:28:32.745 CPU0: JIT: flushing data structures (compiled pages=573)
Mar 09 09:28:32.964 CPU0: MTS: read  access to undefined address 0x3c08002c at pc=0x60819f48 (size=1)
Mar 09 09:28:33.214 CPU0: MTS: read  access to undefined address 0x3c08002c at pc=0x60819f48 (size=1)
Mar 09 09:28:33.479 CPU0: MTS: read  access to undefined address 0x3c08002c at pc=0x60819f48 (size=1)
Mar 09 09:28:33.698 CPU0: MTS: read  access to undefined address 0x3c08002c at pc=0x60819f48 (size=1)
Mar 09 09:28:33.886 CPU0: JIT: partial JIT flush (count=191)
Mar 09 09:28:33.979 CPU0: MTS: read  access to undefined address 0x3c08002c at pc=0x60819f48 (size=1)
Mar 09 09:28:34.229 CPU0: MTS: read  access to undefined address 0x3c08002c at pc=0x60819f48 (size=1)
Mar 09 09:28:34.479 CPU0: MTS: read  access to undefined address 0x3c08002c at pc=0x60819f48 (size=1)
Mar 09 09:28:34.706 CPU0: MTS: read  access to undefined address 0x3c08002c at pc=0x60819f48 (size=1)
Mar 09 09:28:34.956 CPU0: MTS: read  access to undefined address 0x3c08002c at pc=0x60819f48 (size=1)
Mar 09 09:28:35.206 CPU0: MTS: read  access to undefined address 0x3c08002c at pc=0x60819f48 (size=1)
Mar 09 09:28:35.456 CPU0: MTS: read  access to undefined address 0x3c08002c at pc=0x60819f48 (size=1)
Mar 09 09:28:35.713 CPU0: MTS: read  access to undefined address 0x3c08002c at pc=0x60819f48 (size=1)
Mar 09 09:28:35.963 CPU0: MTS: read  access to undefined address 0x3c08002c at pc=0x60819f48 (size=1)
Mar 09 09:28:36.213 CPU0: MTS: read  access to undefined address 0x3c08002c at pc=0x60819f48 (size=1)
Mar 09 09:28:36.463 CPU0: MTS: read  access to undefined address 0x3c08002c at pc=0x60819f48 (size=1)
Mar 09 09:28:36.721 CPU0: MTS: read  access to undefined address 0x3c08002c at pc=0x60819f48 (size=1)
Mar 09 09:28:36.971 CPU0: MTS: read  access to undefined address 0x3c08002c at pc=0x60819f48 (size=1)
Mar 09 09:28:37.221 CPU0: MTS: read  access to undefined address 0x3c08002c at pc=0x60819f48 (size=1)
Mar 09 09:28:37.471 CPU0: MTS: read  access to undefined address 0x3c08002c at pc=0x60819f48 (size=1)
Mar 09 09:28:37.728 CPU0: MTS: read  access to undefined address 0x3c08002c at pc=0x60819f48 (size=1)
Mar 09 09:28:37.978 CPU0: MTS: read  access to undefined address 0x3c08002c at pc=0x60819f48 (size=1)
Mar 09 09:28:38.228 CPU0: MTS: read  access to undefined address 0x3c08002c at pc=0x60819f48 (size=1)
Mar 09 09:28:38.478 CPU0: MTS: read  access to undefined address 0x3c08002c at pc=0x60819f48 (size=1)
Mar 09 09:28:38.572 CPU0: JIT: flushing data structures (compiled pages=568)
Mar 09 09:28:38.719 CPU0: MTS: read  access to undefined address 0x3c08002c at pc=0x60819f48 (size=1)
Mar 09 09:28:38.985 CPU0: MTS: read  access to undefined address 0x3c08002c at pc=0x60819f48 (size=1)
Mar 09 09:28:39.204 CPU0: MTS: read  access to undefined address 0x3c08002c at pc=0x60819f48 (size=1)
Mar 09 09:28:39.423 CPU0: JIT: partial JIT flush (count=201)
Mar 09 09:28:39.454 CPU0: MTS: read  access to undefined address 0x3c08002c at pc=0x60819f48 (size=1)
Mar 09 09:28:39.716 CPU0: MTS: read  access to undefined address 0x3c08002c at pc=0x60819f48 (size=1)
Mar 09 09:28:39.974 CPU0: MTS: read  access to undefined address 0x3c08002c at pc=0x60819f48 (size=1)
Mar 09 09:28:40.209 CPU0: MTS: read  access to undefined address 0x3c08002c at pc=0x60819f48 (size=1)
Mar 09 09:28:40.459 CPU0: MTS: read  access to undefined address 0x3c08002c at pc=0x60819f48 (size=1)
Mar 09 09:28:40.709 CPU0: MTS: read  access to undefined address 0x3c08002c at pc=0x60819f48 (size=1)
Mar 09 09:28:40.959 CPU0: MTS: read  access to undefined address 0x3c08002c at pc=0x60819f48 (size=1)
Mar 09 09:28:41.222 CPU0: MTS: read  access to undefined address 0x3c08002c at pc=0x60819f48 (size=1)
Mar 09 09:28:41.472 CPU0: MTS: read  access to undefined address 0x3c08002c at pc=0x60819f48 (size=1)
Mar 09 09:28:41.697 CPU0: MTS: read  access to undefined address 0x3c08002c at pc=0x60819f48 (size=1)
Mar 09 09:28:41.979 CPU0: MTS: read  access to undefined address 0x3c08002c at pc=0x60819f48 (size=1)
Mar 09 09:28:42.057 C3745_STOP: stopping simulation.
Mar 09 09:28:42.057 CPU0: CPU_STATE: Halting CPU (old state=0)...
Mar 09 09:28:42.166 DEVICE: Removal of device WIC-1T(0), fd=-1, host_addr=0x0, flags=0
Mar 09 09:28:42.197 VM: shutdown procedure engaged.
Mar 09 09:28:42.197 VM_OBJECT: Shutdown of object "slot1"
Mar 09 09:28:42.197 DEVICE: Removal of device slot1, fd=-1, host_addr=0x0, flags=2
Mar 09 09:28:42.197 VM_OBJECT: Shutdown of object "slot0"
Mar 09 09:28:42.197 DEVICE: Removal of device slot0, fd=-1, host_addr=0x0, flags=2
Mar 09 09:28:42.197 VM_OBJECT: Shutdown of object "ns16552"
Mar 09 09:28:42.197 DEVICE: Removal of device ns16552, fd=-1, host_addr=0x0, flags=0
Mar 09 09:28:42.197 VM_OBJECT: Shutdown of object "mem_bswap"
Mar 09 09:28:42.197 DEVICE: Removal of device mem_bswap, fd=-1, host_addr=0x0, flags=0
Mar 09 09:28:42.197 VM_OBJECT: Shutdown of object "rom"
Mar 09 09:28:42.197 DEVICE: Removal of device rom, fd=15, host_addr=0xed760000, flags=1
Mar 09 09:28:42.197 MMAP: unmapping of device 'rom', fd=15, host_addr=0xed760000, len=0x200000
Mar 09 09:28:42.197 VM_OBJECT: Shutdown of object "ram"
Mar 09 09:28:42.197 DEVICE: Removal of device ram, fd=14, host_addr=0xed960000, flags=34
Mar 09 09:28:42.197 MMAP: unmapping of device 'ram', fd=14, host_addr=0xed960000, len=0x10000000
Mar 09 09:28:42.291 VM_OBJECT: Shutdown of object "gt96100"
Mar 09 09:28:42.291 DEVICE: Removal of device gt96100, fd=-1, host_addr=0x0, flags=0
Mar 09 09:28:42.291 VM_OBJECT: Shutdown of object "io_fpga"
Mar 09 09:28:42.291 DEVICE: Removal of device io_fpga, fd=-1, host_addr=0x0, flags=0
Mar 09 09:28:42.291 VM_OBJECT: Shutdown of object "ssa"
Mar 09 09:28:42.291 DEVICE: Removal of device ssa, fd=13, host_addr=0xfd960000, flags=2
Mar 09 09:28:42.291 MMAP: unmapping of device 'ssa', fd=13, host_addr=0xfd960000, len=0x7000
Mar 09 09:28:42.291 VM_OBJECT: Shutdown of object "remote_ctrl"
Mar 09 09:28:42.291 DEVICE: Removal of device remote_ctrl, fd=-1, host_addr=0x0, flags=0
Mar 09 09:28:42.291 VM: removing PCI busses.
Mar 09 09:28:42.291 VM: deleting VTTY.
Mar 09 09:28:42.291 VTTY: Console port: closing FD 12
Mar 09 09:28:42.291 VM: deleting system CPUs.
Mar 09 09:28:42.291 CPU0: CPU_STATE: Halting CPU (old state=1)...
Mar 09 09:28:42.307 VM: shutdown procedure completed.
Mar 09 09:28:42.354 VM: trying to shutdown an inactive VM.