Mar 09 09:28:02.525 VTTY: Console port: waiting connection on tcp port 2006 for protocol IPv4 (FD 11) Mar 09 09:28:02.541 slot0: C/H/S settings = 0/4/32 Mar 09 09:28:02.541 slot1: C/H/S settings = 0/4/32 Mar 09 09:28:02.872 C3745_BOOT: starting instance (CPU0 PC=0xffffffffbfc00000,idle_pc=0x60aa5f14,JIT on) Mar 09 09:28:02.872 CPU0: CPU_STATE: Starting CPU (old state=2)... Mar 09 09:28:02.934 ROM: Microcode has started. Mar 09 09:28:02.934 ROM: trying to read bootvar 'WARM_REBOOT' Mar 09 09:28:02.934 CPU0: IO_FPGA: write to unknown addr 0x30, value=0x0, pc=0xffffffff80a9d228 (size=1) Mar 09 09:28:02.934 CPU0: IO_FPGA: read from unknown addr 0x30, pc=0xffffffff80a9d23c (size=1) Mar 09 09:28:03.130 CPU0: IO_FPGA: read from unknown addr 0x6, pc=0x6026eef8 (size=2) Mar 09 09:28:03.132 CPU0: IO_FPGA: read from unknown addr 0x10000a, pc=0x60276800 (size=2) Mar 09 09:28:03.132 CPU0: IO_FPGA: write to unknown addr 0x10000a, value=0x0, pc=0x60276810 (size=2) Mar 09 09:28:03.132 ROM: unhandled syscall 0x00000047 at pc=0x60a9e9bc (a1=0x80007dac,a2=0x00000010,a3=0xbfb00000) Mar 09 09:28:04.026 ROM: trying to read bootvar 'RANDOM_NUM' Mar 09 09:28:04.073 CPU0: IO_FPGA: write to unknown addr 0x2e, value=0x20, pc=0x60283d28 (size=2) Mar 09 09:28:04.074 CPU0: PCI: read request for device 'gt96100' at pc=0x60286c50: bus=0,device=0,function=0,reg=0x00 Mar 09 09:28:04.074 CPU0: PCI: read request for device 'gt96100' at pc=0x60286c54: bus=0,device=0,function=0,reg=0x00 Mar 09 09:28:04.074 CPU0: PCI: read request for device 'gt96100' at pc=0x60286a04: bus=0,device=0,function=0,reg=0x08 Mar 09 09:28:04.074 CPU0: PCI: write request (data=0x00000000) for device 'gt96100' at pc=0x60286b4c: bus=0,device=0,function=0,reg=0x10 Mar 09 09:28:04.074 CPU0: PCI: write request (data=0x00000000) for device 'gt96100' at pc=0x60286b50: bus=0,device=0,function=0,reg=0x10 Mar 09 09:28:04.074 CPU0: PCI: write request (data=0x00000000) for device 'gt96100' at pc=0x60286b4c: bus=0,device=0,function=0,reg=0x90 Mar 09 09:28:04.074 CPU0: PCI: write request (data=0x00000000) for device 'gt96100' at pc=0x60286b50: bus=0,device=0,function=0,reg=0x90 Mar 09 09:28:04.074 CPU0: PCI: write request (data=0x10000000) for device 'gt96100' at pc=0x60286b4c: bus=0,device=0,function=0,reg=0x14 Mar 09 09:28:04.074 CPU0: PCI: write request (data=0x10000000) for device 'gt96100' at pc=0x60286b50: bus=0,device=0,function=0,reg=0x14 Mar 09 09:28:04.074 CPU0: PCI: write request (data=0x10000000) for device 'gt96100' at pc=0x60286b4c: bus=0,device=0,function=0,reg=0x94 Mar 09 09:28:04.074 CPU0: PCI: write request (data=0x10000000) for device 'gt96100' at pc=0x60286b50: bus=0,device=0,function=0,reg=0x94 Mar 09 09:28:04.074 CPU0: PCI: write request (data=0x04000000) for device 'gt96100' at pc=0x60286b4c: bus=0,device=0,function=0,reg=0x20 Mar 09 09:28:04.074 CPU0: PCI: write request (data=0x04000000) for device 'gt96100' at pc=0x60286b50: bus=0,device=0,function=0,reg=0x20 Mar 09 09:28:04.074 CPU0: PCI: write request (data=0x04000000) for device 'gt96100' at pc=0x60286b4c: bus=0,device=0,function=0,reg=0xa0 Mar 09 09:28:04.074 CPU0: PCI: write request (data=0x04000000) for device 'gt96100' at pc=0x60286b50: bus=0,device=0,function=0,reg=0xa0 Mar 09 09:28:04.074 CPU0: PCI: write request (data=0x00000146) for device 'gt96100' at pc=0x60286b4c: bus=0,device=0,function=0,reg=0x04 Mar 09 09:28:04.074 CPU0: PCI: write request (data=0x00000146) for device 'gt96100' at pc=0x60286b50: bus=0,device=0,function=0,reg=0x04 Mar 09 09:28:04.074 CPU0: PCI: write request (data=0x00000146) for device 'gt96100' at pc=0x60286b4c: bus=0,device=0,function=0,reg=0x84 Mar 09 09:28:04.074 CPU0: PCI: write request (data=0x00000146) for device 'gt96100' at pc=0x60286b50: bus=0,device=0,function=0,reg=0x84 Mar 09 09:28:04.074 CPU0: PCI: write request (data=0x00000007) for device 'gt96100' at pc=0x60286b4c: bus=0,device=0,function=0,reg=0x0c Mar 09 09:28:04.074 CPU0: PCI: write request (data=0x00000007) for device 'gt96100' at pc=0x60286b50: bus=0,device=0,function=0,reg=0x0c Mar 09 09:28:04.074 CPU0: PCI: write request (data=0x00000007) for device 'gt96100' at pc=0x60286b4c: bus=0,device=0,function=0,reg=0x8c Mar 09 09:28:04.074 CPU0: PCI: write request (data=0x00000007) for device 'gt96100' at pc=0x60286b50: bus=0,device=0,function=0,reg=0x8c Mar 09 09:28:04.074 CPU0: PCI: write request (data=0x00000000) for device 'gt96100' at pc=0x60286b4c: bus=0,device=0,function=0,reg=0x10 Mar 09 09:28:04.074 CPU0: PCI: write request (data=0x00000000) for device 'gt96100' at pc=0x60286b50: bus=0,device=0,function=0,reg=0x10 Mar 09 09:28:04.074 CPU0: PCI: write request (data=0x00000000) for device 'gt96100' at pc=0x60286b4c: bus=0,device=0,function=0,reg=0x90 Mar 09 09:28:04.074 CPU0: PCI: write request (data=0x00000000) for device 'gt96100' at pc=0x60286b50: bus=0,device=0,function=0,reg=0x90 Mar 09 09:28:04.074 CPU0: PCI: write request (data=0x20000000) for device 'gt96100' at pc=0x60286b4c: bus=0,device=0,function=0,reg=0x14 Mar 09 09:28:04.074 CPU0: PCI: write request (data=0x20000000) for device 'gt96100' at pc=0x60286b50: bus=0,device=0,function=0,reg=0x14 Mar 09 09:28:04.074 CPU0: PCI: write request (data=0x20000000) for device 'gt96100' at pc=0x60286b4c: bus=0,device=0,function=0,reg=0x94 Mar 09 09:28:04.074 CPU0: PCI: write request (data=0x20000000) for device 'gt96100' at pc=0x60286b50: bus=0,device=0,function=0,reg=0x94 Mar 09 09:28:04.074 CPU0: PCI: write request (data=0xc0000000) for unknown device at pc=0x60286b4c (bus=0,device=0,function=1,reg=0x10). Mar 09 09:28:04.074 CPU0: PCI: write request (data=0xc0000000) for unknown device at pc=0x60286b50 (bus=0,device=0,function=1,reg=0x10). Mar 09 09:28:04.074 CPU0: PCI: write request (data=0xc0000000) for unknown device at pc=0x60286b4c (bus=0,device=0,function=1,reg=0x90). Mar 09 09:28:04.074 CPU0: PCI: write request (data=0xc0000000) for unknown device at pc=0x60286b50 (bus=0,device=0,function=1,reg=0x90). Mar 09 09:28:04.075 CPU0: PCI: write request (data=0xe0000000) for unknown device at pc=0x60286b4c (bus=0,device=0,function=1,reg=0x14). Mar 09 09:28:04.075 CPU0: PCI: write request (data=0xe0000000) for unknown device at pc=0x60286b50 (bus=0,device=0,function=1,reg=0x14). Mar 09 09:28:04.075 CPU0: PCI: write request (data=0xe0000000) for unknown device at pc=0x60286b4c (bus=0,device=0,function=1,reg=0x94). Mar 09 09:28:04.075 CPU0: PCI: write request (data=0xe0000000) for unknown device at pc=0x60286b50 (bus=0,device=0,function=1,reg=0x94). Mar 09 09:28:04.075 CPU0: IO_FPGA: write to unknown addr 0x4c, value=0xf000, pc=0x6028436c (size=2) Mar 09 09:28:04.075 CPU0: PCI: read request for device 'ti2050b' at pc=0x60286c60: bus=0,device=1,function=0,reg=0x00 Mar 09 09:28:04.075 CPU0: PCI: read request for device 'ti2050b' at pc=0x60286c64: bus=0,device=1,function=0,reg=0x00 Mar 09 09:28:04.075 CPU0: PCI: read request for device 'ti2050b' at pc=0x60286c60: bus=0,device=1,function=0,reg=0x40 Mar 09 09:28:04.075 CPU0: PCI: read request for device 'ti2050b' at pc=0x60286c64: bus=0,device=1,function=0,reg=0x40 Mar 09 09:28:04.075 CPU0: PCI: write request (data=0xffff0000) for device 'ti2050b' at pc=0x60286b2c: bus=0,device=1,function=0,reg=0x04 Mar 09 09:28:04.075 CPU0: PCI: write request (data=0xffff0000) for device 'ti2050b' at pc=0x60286b38: bus=0,device=1,function=0,reg=0x04 Mar 09 09:28:04.075 CPU0: PCI: write request (data=0x0000f810) for device 'ti2050b' at pc=0x60286b2c: bus=0,device=1,function=0,reg=0x0c Mar 09 09:28:04.075 CPU0: PCI: write request (data=0x0000f810) for device 'ti2050b' at pc=0x60286b38: bus=0,device=1,function=0,reg=0x0c Mar 09 09:28:04.075 CPU0: PCI: write request (data=0x00040100) for device 'ti2050b' at pc=0x60286b2c: bus=0,device=1,function=0,reg=0x18 Mar 09 09:28:04.076 PCI: PCI bridge 0,1,0 -> pri: 00, sec: 01, sub: 04 Mar 09 09:28:04.076 CPU0: PCI: write request (data=0x00040100) for device 'ti2050b' at pc=0x60286b38: bus=0,device=1,function=0,reg=0x18 Mar 09 09:28:04.076 PCI: PCI bridge 0,1,0 -> pri: 00, sec: 01, sub: 04 Mar 09 09:28:04.076 CPU0: PCI: write request (data=0x02801f00) for device 'ti2050b' at pc=0x60286b2c: bus=0,device=1,function=0,reg=0x1c Mar 09 09:28:04.076 CPU0: PCI: write request (data=0x02801f00) for device 'ti2050b' at pc=0x60286b38: bus=0,device=1,function=0,reg=0x1c Mar 09 09:28:04.076 CPU0: PCI: write request (data=0x4d704d00) for device 'ti2050b' at pc=0x60286b2c: bus=0,device=1,function=0,reg=0x20 Mar 09 09:28:04.076 CPU0: PCI: write request (data=0x4d704d00) for device 'ti2050b' at pc=0x60286b38: bus=0,device=1,function=0,reg=0x20 Mar 09 09:28:04.076 CPU0: PCI: write request (data=0x00014d01) for device 'ti2050b' at pc=0x60286b2c: bus=0,device=1,function=0,reg=0x24 Mar 09 09:28:04.076 CPU0: PCI: write request (data=0x00014d01) for device 'ti2050b' at pc=0x60286b38: bus=0,device=1,function=0,reg=0x24 Mar 09 09:28:04.076 CPU0: PCI: write request (data=0x00200020) for device 'ti2050b' at pc=0x60286b2c: bus=0,device=1,function=0,reg=0x30 Mar 09 09:28:04.076 CPU0: PCI: write request (data=0x00200020) for device 'ti2050b' at pc=0x60286b38: bus=0,device=1,function=0,reg=0x30 Mar 09 09:28:04.076 CPU0: PCI: write request (data=0x03000000) for device 'ti2050b' at pc=0x60286b2c: bus=0,device=1,function=0,reg=0x3c Mar 09 09:28:04.076 CPU0: PCI: write request (data=0x03000000) for device 'ti2050b' at pc=0x60286b38: bus=0,device=1,function=0,reg=0x3c Mar 09 09:28:04.076 CPU0: PCI: write request (data=0x00000000) for device 'ti2050b' at pc=0x60286b2c: bus=0,device=1,function=0,reg=0x40 Mar 09 09:28:04.076 CPU0: PCI: write request (data=0x00000000) for device 'ti2050b' at pc=0x60286b38: bus=0,device=1,function=0,reg=0x40 Mar 09 09:28:04.076 CPU0: PCI: write request (data=0x00000000) for device 'ti2050b' at pc=0x60286b2c: bus=0,device=1,function=0,reg=0x64 Mar 09 09:28:04.076 CPU0: PCI: write request (data=0x00000000) for device 'ti2050b' at pc=0x60286b38: bus=0,device=1,function=0,reg=0x64 Mar 09 09:28:04.076 CPU0: PCI: write request (data=0x00000000) for device 'ti2050b' at pc=0x60286b2c: bus=0,device=1,function=0,reg=0x68 Mar 09 09:28:04.076 CPU0: PCI: write request (data=0x00000000) for device 'ti2050b' at pc=0x60286b38: bus=0,device=1,function=0,reg=0x68 Mar 09 09:28:04.076 CPU0: PCI: write request (data=0x00000007) for device 'ti2050b' at pc=0x60286b2c: bus=0,device=1,function=0,reg=0x04 Mar 09 09:28:04.076 CPU0: PCI: write request (data=0x00000007) for device 'ti2050b' at pc=0x60286b38: bus=0,device=1,function=0,reg=0x04 Mar 09 09:28:04.076 CPU0: PCI: write request (data=0x00000001) for device 'ti2050b' at pc=0x60286b2c: bus=0,device=1,function=0,reg=0xf0 Mar 09 09:28:04.076 CPU0: PCI: write request (data=0x00000001) for device 'ti2050b' at pc=0x60286b38: bus=0,device=1,function=0,reg=0xf0 Mar 09 09:28:04.076 CPU0: PCI: read request for device 'ti2050b' at pc=0x60286c60: bus=0,device=2,function=0,reg=0x00 Mar 09 09:28:04.076 CPU0: PCI: read request for device 'ti2050b' at pc=0x60286c64: bus=0,device=2,function=0,reg=0x00 Mar 09 09:28:04.076 CPU0: PCI: read request for device 'ti2050b' at pc=0x60286c60: bus=0,device=2,function=0,reg=0x40 Mar 09 09:28:04.076 CPU0: PCI: read request for device 'ti2050b' at pc=0x60286c64: bus=0,device=2,function=0,reg=0x40 Mar 09 09:28:04.076 CPU0: PCI: write request (data=0xffff0000) for device 'ti2050b' at pc=0x60286b2c: bus=0,device=2,function=0,reg=0x04 Mar 09 09:28:04.076 CPU0: PCI: write request (data=0xffff0000) for device 'ti2050b' at pc=0x60286b38: bus=0,device=2,function=0,reg=0x04 Mar 09 09:28:04.076 CPU0: PCI: write request (data=0x0000f810) for device 'ti2050b' at pc=0x60286b2c: bus=0,device=2,function=0,reg=0x0c Mar 09 09:28:04.076 CPU0: PCI: write request (data=0x0000f810) for device 'ti2050b' at pc=0x60286b38: bus=0,device=2,function=0,reg=0x0c Mar 09 09:28:04.076 CPU0: PCI: write request (data=0x00080500) for device 'ti2050b' at pc=0x60286b2c: bus=0,device=2,function=0,reg=0x18 Mar 09 09:28:04.076 PCI: PCI bridge 0,2,0 -> pri: 00, sec: 05, sub: 08 Mar 09 09:28:04.076 CPU0: PCI: write request (data=0x00080500) for device 'ti2050b' at pc=0x60286b38: bus=0,device=2,function=0,reg=0x18 Mar 09 09:28:04.076 PCI: PCI bridge 0,2,0 -> pri: 00, sec: 05, sub: 08 Mar 09 09:28:04.076 CPU0: PCI: write request (data=0x02803f20) for device 'ti2050b' at pc=0x60286b2c: bus=0,device=2,function=0,reg=0x1c Mar 09 09:28:04.076 CPU0: PCI: write request (data=0x02803f20) for device 'ti2050b' at pc=0x60286b38: bus=0,device=2,function=0,reg=0x1c Mar 09 09:28:04.076 CPU0: PCI: write request (data=0x4df04d80) for device 'ti2050b' at pc=0x60286b2c: bus=0,device=2,function=0,reg=0x20 Mar 09 09:28:04.076 CPU0: PCI: write request (data=0x4df04d80) for device 'ti2050b' at pc=0x60286b38: bus=0,device=2,function=0,reg=0x20 Mar 09 09:28:04.076 CPU0: PCI: write request (data=0x00014d81) for device 'ti2050b' at pc=0x60286b2c: bus=0,device=2,function=0,reg=0x24 Mar 09 09:28:04.076 CPU0: PCI: write request (data=0x00014d81) for device 'ti2050b' at pc=0x60286b38: bus=0,device=2,function=0,reg=0x24 Mar 09 09:28:04.076 CPU0: PCI: write request (data=0x00200020) for device 'ti2050b' at pc=0x60286b2c: bus=0,device=2,function=0,reg=0x30 Mar 09 09:28:04.076 CPU0: PCI: write request (data=0x00200020) for device 'ti2050b' at pc=0x60286b38: bus=0,device=2,function=0,reg=0x30 Mar 09 09:28:04.076 CPU0: PCI: write request (data=0x03000000) for device 'ti2050b' at pc=0x60286b2c: bus=0,device=2,function=0,reg=0x3c Mar 09 09:28:04.076 CPU0: PCI: write request (data=0x03000000) for device 'ti2050b' at pc=0x60286b38: bus=0,device=2,function=0,reg=0x3c Mar 09 09:28:04.076 CPU0: PCI: write request (data=0x00000000) for device 'ti2050b' at pc=0x60286b2c: bus=0,device=2,function=0,reg=0x40 Mar 09 09:28:04.076 CPU0: PCI: write request (data=0x00000000) for device 'ti2050b' at pc=0x60286b38: bus=0,device=2,function=0,reg=0x40 Mar 09 09:28:04.076 CPU0: PCI: write request (data=0x00000000) for device 'ti2050b' at pc=0x60286b2c: bus=0,device=2,function=0,reg=0x64 Mar 09 09:28:04.076 CPU0: PCI: write request (data=0x00000000) for device 'ti2050b' at pc=0x60286b38: bus=0,device=2,function=0,reg=0x64 Mar 09 09:28:04.076 CPU0: PCI: write request (data=0x00000000) for device 'ti2050b' at pc=0x60286b2c: bus=0,device=2,function=0,reg=0x68 Mar 09 09:28:04.076 CPU0: PCI: write request (data=0x00000000) for device 'ti2050b' at pc=0x60286b38: bus=0,device=2,function=0,reg=0x68 Mar 09 09:28:04.076 CPU0: PCI: write request (data=0x00000007) for device 'ti2050b' at pc=0x60286b2c: bus=0,device=2,function=0,reg=0x04 Mar 09 09:28:04.076 CPU0: PCI: write request (data=0x00000007) for device 'ti2050b' at pc=0x60286b38: bus=0,device=2,function=0,reg=0x04 Mar 09 09:28:04.076 CPU0: PCI: write request (data=0x00000001) for device 'ti2050b' at pc=0x60286b2c: bus=0,device=2,function=0,reg=0xf0 Mar 09 09:28:04.081 CPU0: PCI: write request (data=0x00000001) for device 'ti2050b' at pc=0x60286b38: bus=0,device=2,function=0,reg=0xf0 Mar 09 09:28:04.081 CPU0: PCI: read request for device 'ti2050b' at pc=0x60286c60: bus=0,device=3,function=0,reg=0x00 Mar 09 09:28:04.081 CPU0: PCI: read request for device 'ti2050b' at pc=0x60286c64: bus=0,device=3,function=0,reg=0x00 Mar 09 09:28:04.081 CPU0: PCI: read request for device 'ti2050b' at pc=0x60286c60: bus=0,device=3,function=0,reg=0x40 Mar 09 09:28:04.081 CPU0: PCI: read request for device 'ti2050b' at pc=0x60286c64: bus=0,device=3,function=0,reg=0x40 Mar 09 09:28:04.081 CPU0: PCI: write request (data=0xffff0000) for device 'ti2050b' at pc=0x60286b2c: bus=0,device=3,function=0,reg=0x04 Mar 09 09:28:04.081 CPU0: PCI: write request (data=0xffff0000) for device 'ti2050b' at pc=0x60286b38: bus=0,device=3,function=0,reg=0x04 Mar 09 09:28:04.081 CPU0: PCI: write request (data=0x0000f810) for device 'ti2050b' at pc=0x60286b2c: bus=0,device=3,function=0,reg=0x0c Mar 09 09:28:04.081 CPU0: PCI: write request (data=0x0000f810) for device 'ti2050b' at pc=0x60286b38: bus=0,device=3,function=0,reg=0x0c Mar 09 09:28:04.081 CPU0: PCI: write request (data=0x000c0900) for device 'ti2050b' at pc=0x60286b2c: bus=0,device=3,function=0,reg=0x18 Mar 09 09:28:04.081 PCI: PCI bridge 0,3,0 -> pri: 00, sec: 09, sub: 12 Mar 09 09:28:04.081 CPU0: PCI: write request (data=0x000c0900) for device 'ti2050b' at pc=0x60286b38: bus=0,device=3,function=0,reg=0x18 Mar 09 09:28:04.081 PCI: PCI bridge 0,3,0 -> pri: 00, sec: 09, sub: 12 Mar 09 09:28:04.081 CPU0: PCI: write request (data=0x02809f80) for device 'ti2050b' at pc=0x60286b2c: bus=0,device=3,function=0,reg=0x1c Mar 09 09:28:04.081 CPU0: PCI: write request (data=0x02809f80) for device 'ti2050b' at pc=0x60286b38: bus=0,device=3,function=0,reg=0x1c Mar 09 09:28:04.081 CPU0: PCI: write request (data=0x4e704e00) for device 'ti2050b' at pc=0x60286b2c: bus=0,device=3,function=0,reg=0x20 Mar 09 09:28:04.081 CPU0: PCI: write request (data=0x4e704e00) for device 'ti2050b' at pc=0x60286b38: bus=0,device=3,function=0,reg=0x20 Mar 09 09:28:04.081 CPU0: PCI: write request (data=0x00014e01) for device 'ti2050b' at pc=0x60286b2c: bus=0,device=3,function=0,reg=0x24 Mar 09 09:28:04.081 CPU0: PCI: write request (data=0x00014e01) for device 'ti2050b' at pc=0x60286b38: bus=0,device=3,function=0,reg=0x24 Mar 09 09:28:04.081 CPU0: PCI: write request (data=0x00200020) for device 'ti2050b' at pc=0x60286b2c: bus=0,device=3,function=0,reg=0x30 Mar 09 09:28:04.081 CPU0: PCI: write request (data=0x00200020) for device 'ti2050b' at pc=0x60286b38: bus=0,device=3,function=0,reg=0x30 Mar 09 09:28:04.081 CPU0: PCI: write request (data=0x03000000) for device 'ti2050b' at pc=0x60286b2c: bus=0,device=3,function=0,reg=0x3c Mar 09 09:28:04.081 CPU0: PCI: write request (data=0x03000000) for device 'ti2050b' at pc=0x60286b38: bus=0,device=3,function=0,reg=0x3c Mar 09 09:28:04.081 CPU0: PCI: write request (data=0x00000000) for device 'ti2050b' at pc=0x60286b2c: bus=0,device=3,function=0,reg=0x40 Mar 09 09:28:04.081 CPU0: PCI: write request (data=0x00000000) for device 'ti2050b' at pc=0x60286b38: bus=0,device=3,function=0,reg=0x40 Mar 09 09:28:04.081 CPU0: PCI: write request (data=0x00000000) for device 'ti2050b' at pc=0x60286b2c: bus=0,device=3,function=0,reg=0x64 Mar 09 09:28:04.081 CPU0: PCI: write request (data=0x00000000) for device 'ti2050b' at pc=0x60286b38: bus=0,device=3,function=0,reg=0x64 Mar 09 09:28:04.081 CPU0: PCI: write request (data=0x00000000) for device 'ti2050b' at pc=0x60286b2c: bus=0,device=3,function=0,reg=0x68 Mar 09 09:28:04.081 CPU0: PCI: write request (data=0x00000000) for device 'ti2050b' at pc=0x60286b38: bus=0,device=3,function=0,reg=0x68 Mar 09 09:28:04.081 CPU0: PCI: write request (data=0x00000007) for device 'ti2050b' at pc=0x60286b2c: bus=0,device=3,function=0,reg=0x04 Mar 09 09:28:04.081 CPU0: PCI: write request (data=0x00000007) for device 'ti2050b' at pc=0x60286b38: bus=0,device=3,function=0,reg=0x04 Mar 09 09:28:04.081 CPU0: PCI: write request (data=0x00000001) for device 'ti2050b' at pc=0x60286b2c: bus=0,device=3,function=0,reg=0xf0 Mar 09 09:28:04.081 CPU0: PCI: write request (data=0x00000001) for device 'ti2050b' at pc=0x60286b38: bus=0,device=3,function=0,reg=0xf0 Mar 09 09:28:04.081 CPU0: PCI: read request for device 'ti2050b' at pc=0x60286c60: bus=0,device=4,function=0,reg=0x00 Mar 09 09:28:04.081 CPU0: PCI: read request for device 'ti2050b' at pc=0x60286c64: bus=0,device=4,function=0,reg=0x00 Mar 09 09:28:04.081 CPU0: PCI: read request for device 'ti2050b' at pc=0x60286c60: bus=0,device=4,function=0,reg=0x40 Mar 09 09:28:04.081 CPU0: PCI: read request for device 'ti2050b' at pc=0x60286c64: bus=0,device=4,function=0,reg=0x40 Mar 09 09:28:04.081 CPU0: PCI: write request (data=0xffff0000) for device 'ti2050b' at pc=0x60286b2c: bus=0,device=4,function=0,reg=0x04 Mar 09 09:28:04.081 CPU0: PCI: write request (data=0xffff0000) for device 'ti2050b' at pc=0x60286b38: bus=0,device=4,function=0,reg=0x04 Mar 09 09:28:04.081 CPU0: PCI: write request (data=0x0000f810) for device 'ti2050b' at pc=0x60286b2c: bus=0,device=4,function=0,reg=0x0c Mar 09 09:28:04.081 CPU0: PCI: write request (data=0x0000f810) for device 'ti2050b' at pc=0x60286b38: bus=0,device=4,function=0,reg=0x0c Mar 09 09:28:04.081 CPU0: PCI: write request (data=0x00100d00) for device 'ti2050b' at pc=0x60286b2c: bus=0,device=4,function=0,reg=0x18 Mar 09 09:28:04.081 PCI: PCI bridge 0,4,0 -> pri: 00, sec: 13, sub: 16 Mar 09 09:28:04.081 CPU0: PCI: write request (data=0x00100d00) for device 'ti2050b' at pc=0x60286b38: bus=0,device=4,function=0,reg=0x18 Mar 09 09:28:04.081 PCI: PCI bridge 0,4,0 -> pri: 00, sec: 13, sub: 16 Mar 09 09:28:04.081 CPU0: PCI: write request (data=0x0280bfa0) for device 'ti2050b' at pc=0x60286b2c: bus=0,device=4,function=0,reg=0x1c Mar 09 09:28:04.081 CPU0: PCI: write request (data=0x0280bfa0) for device 'ti2050b' at pc=0x60286b38: bus=0,device=4,function=0,reg=0x1c Mar 09 09:28:04.081 CPU0: PCI: write request (data=0x4ef04e80) for device 'ti2050b' at pc=0x60286b2c: bus=0,device=4,function=0,reg=0x20 Mar 09 09:28:04.081 CPU0: PCI: write request (data=0x4ef04e80) for device 'ti2050b' at pc=0x60286b38: bus=0,device=4,function=0,reg=0x20 Mar 09 09:28:04.081 CPU0: PCI: write request (data=0x00014e81) for device 'ti2050b' at pc=0x60286b2c: bus=0,device=4,function=0,reg=0x24 Mar 09 09:28:04.081 CPU0: PCI: write request (data=0x00014e81) for device 'ti2050b' at pc=0x60286b38: bus=0,device=4,function=0,reg=0x24 Mar 09 09:28:04.081 CPU0: PCI: write request (data=0x00200020) for device 'ti2050b' at pc=0x60286b2c: bus=0,device=4,function=0,reg=0x30 Mar 09 09:28:04.081 CPU0: PCI: write request (data=0x00200020) for device 'ti2050b' at pc=0x60286b38: bus=0,device=4,function=0,reg=0x30 Mar 09 09:28:04.081 CPU0: PCI: write request (data=0x03000000) for device 'ti2050b' at pc=0x60286b2c: bus=0,device=4,function=0,reg=0x3c Mar 09 09:28:04.081 CPU0: PCI: write request (data=0x03000000) for device 'ti2050b' at pc=0x60286b38: bus=0,device=4,function=0,reg=0x3c Mar 09 09:28:04.081 CPU0: PCI: write request (data=0x00000000) for device 'ti2050b' at pc=0x60286b2c: bus=0,device=4,function=0,reg=0x40 Mar 09 09:28:04.081 CPU0: PCI: write request (data=0x00000000) for device 'ti2050b' at pc=0x60286b38: bus=0,device=4,function=0,reg=0x40 Mar 09 09:28:04.081 CPU0: PCI: write request (data=0x00000000) for device 'ti2050b' at pc=0x60286b2c: bus=0,device=4,function=0,reg=0x64 Mar 09 09:28:04.082 CPU0: PCI: write request (data=0x00000000) for device 'ti2050b' at pc=0x60286b38: bus=0,device=4,function=0,reg=0x64 Mar 09 09:28:04.082 CPU0: PCI: write request (data=0x00000000) for device 'ti2050b' at pc=0x60286b2c: bus=0,device=4,function=0,reg=0x68 Mar 09 09:28:04.082 CPU0: PCI: write request (data=0x00000000) for device 'ti2050b' at pc=0x60286b38: bus=0,device=4,function=0,reg=0x68 Mar 09 09:28:04.082 CPU0: PCI: write request (data=0x00000007) for device 'ti2050b' at pc=0x60286b2c: bus=0,device=4,function=0,reg=0x04 Mar 09 09:28:04.082 CPU0: PCI: write request (data=0x00000007) for device 'ti2050b' at pc=0x60286b38: bus=0,device=4,function=0,reg=0x04 Mar 09 09:28:04.082 CPU0: PCI: write request (data=0x00000001) for device 'ti2050b' at pc=0x60286b2c: bus=0,device=4,function=0,reg=0xf0 Mar 09 09:28:04.082 CPU0: PCI: write request (data=0x00000001) for device 'ti2050b' at pc=0x60286b38: bus=0,device=4,function=0,reg=0xf0 Mar 09 09:28:04.082 CPU0: PCI: write request (data=0x24000000) for device 'gt96100' at pc=0x60286b4c: bus=0,device=0,function=0,reg=0x20 Mar 09 09:28:04.082 CPU0: PCI: write request (data=0x24000000) for device 'gt96100' at pc=0x60286b50: bus=0,device=0,function=0,reg=0x20 Mar 09 09:28:04.082 CPU0: PCI: write request (data=0x24000000) for device 'gt96100' at pc=0x60286b4c: bus=0,device=0,function=0,reg=0xa0 Mar 09 09:28:04.082 CPU0: PCI: write request (data=0x24000000) for device 'gt96100' at pc=0x60286b50: bus=0,device=0,function=0,reg=0xa0 Mar 09 09:28:04.082 CPU0: IO_FPGA: read from unknown addr 0x16, pc=0x60276b14 (size=2) Mar 09 09:28:07.689 ROM: unhandled syscall 0x0000003e at pc=0x60a9e9bc (a1=0x80007d9c,a2=0x00002580,a3=0x64590000) Mar 09 09:28:07.689 ROM: unhandled syscall 0x00000047 at pc=0x60a9e9bc (a1=0x80007da4,a2=0x00000000,a3=0x64590000) Mar 09 09:28:08.745 CPU0: JIT: partial JIT flush (count=178) Mar 09 09:28:08.815 CPU0: JIT: flushing data structures (compiled pages=234) Mar 09 09:28:08.877 ROM: trying to read bootvar 'BOOT' Mar 09 09:28:08.877 ROM: trying to read bootvar 'CONFIG_FILE' Mar 09 09:28:08.877 ROM: trying to read bootvar 'BOOTLDR' Mar 09 09:28:08.877 ROM: trying to read bootvar 'RSHELF' Mar 09 09:28:08.877 ROM: trying to read bootvar 'DSHELF' Mar 09 09:28:08.877 ROM: trying to read bootvar 'DSHELFINFO' Mar 09 09:28:08.877 ROM: trying to read bootvar 'RESET_COUNTER' Mar 09 09:28:08.877 ROM: trying to read bootvar 'CHRG_LOCRECSN' Mar 09 09:28:08.877 ROM: trying to read bootvar 'CHRG_ID' Mar 09 09:28:08.877 ROM: trying to read bootvar 'SLOTCACHE' Mar 09 09:28:08.877 ROM: trying to read bootvar 'OVERTEMP' Mar 09 09:28:08.877 ROM: trying to read bootvar 'DIAG' Mar 09 09:28:08.877 ROM: trying to read bootvar 'WARM_REBOOT' Mar 09 09:28:08.908 CPU0: JIT: partial JIT flush (count=179) Mar 09 09:28:09.044 CPU0: JIT: flushing data structures (compiled pages=242) Mar 09 09:28:09.144 CPU0: IO_FPGA: read from unknown addr 0x16, pc=0x60819334 (size=2) Mar 09 09:28:09.145 CPU0: MTS: read access to undefined address 0x3c080022 at pc=0x60818f30 (size=1) Mar 09 09:28:09.145 CPU0: MTS: read access to undefined address 0x3c08002b at pc=0x60818f74 (size=1) Mar 09 09:28:09.145 CPU0: MTS: write access to undefined address 0x3c08002b at pc=0x60818f80, value=0x00000020 (size=1) Mar 09 09:28:09.145 CPU0: MTS: read access to undefined address 0x3c08002b at pc=0x60818f84 (size=1) Mar 09 09:28:09.145 CPU0: MTS: write access to undefined address 0x3c08002b at pc=0x60818f8c, value=0x00000000 (size=1) Mar 09 09:28:09.145 CPU0: MTS: read access to undefined address 0x3c08002b at pc=0x60818f98 (size=1) Mar 09 09:28:09.145 CPU0: MTS: write access to undefined address 0x3c08002b at pc=0x60818fa4, value=0x00000040 (size=1) Mar 09 09:28:09.145 CPU0: MTS: read access to undefined address 0x3c080023 at pc=0x60818fb8 (size=1) Mar 09 09:28:09.145 CPU0: MTS: write access to undefined address 0x3c080023 at pc=0x60818fc4, value=0x00000000 (size=1) Mar 09 09:28:09.145 CPU0: MTS: read access to undefined address 0x3c080023 at pc=0x60818fd0 (size=1) Mar 09 09:28:09.145 CPU0: MTS: write access to undefined address 0x3c080023 at pc=0x60818fe0, value=0x00000080 (size=1) Mar 09 09:28:09.145 CPU0: MTS: read access to undefined address 0x3c000002 at pc=0x6081adac (size=1) Mar 09 09:28:09.145 CPU0: MTS: write access to undefined address 0x3c000002 at pc=0x6081adb8, value=0x00000080 (size=1) Mar 09 09:28:09.145 CPU0: MTS: read access to undefined address 0x3c000002 at pc=0x6081adbc (size=1) Mar 09 09:28:09.326 CPU0: MTS: read access to undefined address 0x3c000002 at pc=0x6081ade4 (size=1) Mar 09 09:28:09.492 CPU0: MTS: read access to undefined address 0x3c000002 at pc=0x6081ade4 (size=1) Mar 09 09:28:09.627 CPU0: MTS: read access to undefined address 0x3c000002 at pc=0x6081ade4 (size=1) Mar 09 09:28:09.788 CPU0: MTS: read access to undefined address 0x3c000002 at pc=0x6081ade4 (size=1) Mar 09 09:28:09.926 CPU0: MTS: read access to undefined address 0x3c000002 at pc=0x6081ade4 (size=1) Mar 09 09:28:10.070 CPU0: MTS: read access to undefined address 0x3c000002 at pc=0x6081ade4 (size=1) Mar 09 09:28:10.070 CPU0: MTS: write access to undefined address 0x3c080007 at pc=0x608190cc, value=0x00000002 (size=1) Mar 09 09:28:10.070 CPU0: MTS: write access to undefined address 0x3c080008 at pc=0x608190d4, value=0x00000002 (size=1) Mar 09 09:28:10.070 CPU0: MTS: write access to undefined address 0x3c080009 at pc=0x608190dc, value=0x00000002 (size=1) Mar 09 09:28:10.070 CPU0: MTS: write access to undefined address 0x3c08000a at pc=0x608190e0, value=0x00000002 (size=1) Mar 09 09:28:10.070 CPU0: MTS: write access to undefined address 0x3c08000b at pc=0x608190e4, value=0x00000002 (size=1) Mar 09 09:28:10.070 CPU0: MTS: write access to undefined address 0x3c08000c at pc=0x608190e8, value=0x00000002 (size=1) Mar 09 09:28:10.071 CPU0: MTS: read access to undefined address 0x3c080022 at pc=0x60819f6c (size=1) Mar 09 09:28:10.127 CPU0: JIT: partial JIT flush (count=187) Mar 09 09:28:10.184 CPU0: JIT: flushing data structures (compiled pages=253) Mar 09 09:28:10.265 CPU0: IO_FPGA: read from unknown addr 0x10000a, pc=0x60283dd4 (size=2) Mar 09 09:28:10.265 CPU0: IO_FPGA: write to unknown addr 0x10000a, value=0x1000, pc=0x60283ddc (size=2) Mar 09 09:28:10.574 CPU0: PCI: read request for device 'ti2050b' at pc=0x60286c60: bus=0,device=1,function=0,reg=0x3c Mar 09 09:28:10.575 CPU0: PCI: read request for device 'ti2050b' at pc=0x60286c64: bus=0,device=1,function=0,reg=0x3c Mar 09 09:28:10.575 CPU0: PCI: write request (data=0x00400000) for device 'ti2050b' at pc=0x60286b2c: bus=0,device=1,function=0,reg=0x3c Mar 09 09:28:10.575 CPU0: PCI: write request (data=0x00400000) for device 'ti2050b' at pc=0x60286b38: bus=0,device=1,function=0,reg=0x3c Mar 09 09:28:10.575 CPU0: PCI: read request for device 'ti2050b' at pc=0x60286c60: bus=0,device=1,function=0,reg=0x3c Mar 09 09:28:10.575 CPU0: PCI: read request for device 'ti2050b' at pc=0x60286c64: bus=0,device=1,function=0,reg=0x3c Mar 09 09:28:10.575 CPU0: PCI: write request (data=0x00000000) for device 'ti2050b' at pc=0x60286b2c: bus=0,device=1,function=0,reg=0x3c Mar 09 09:28:10.575 CPU0: PCI: write request (data=0x00000000) for device 'ti2050b' at pc=0x60286b38: bus=0,device=1,function=0,reg=0x3c Mar 09 09:28:10.708 CPU0: PCI: read request for device 'ti2050b' at pc=0x60286c60: bus=0,device=1,function=0,reg=0x00 Mar 09 09:28:10.708 CPU0: PCI: read request for device 'ti2050b' at pc=0x60286c64: bus=0,device=1,function=0,reg=0x00 Mar 09 09:28:10.708 CPU0: PCI: read request for device 'ti2050b' at pc=0x60286c60: bus=0,device=1,function=0,reg=0x40 Mar 09 09:28:10.708 CPU0: PCI: read request for device 'ti2050b' at pc=0x60286c64: bus=0,device=1,function=0,reg=0x40 Mar 09 09:28:10.708 CPU0: PCI: write request (data=0xffff0000) for device 'ti2050b' at pc=0x60286b2c: bus=0,device=1,function=0,reg=0x04 Mar 09 09:28:10.708 CPU0: PCI: write request (data=0xffff0000) for device 'ti2050b' at pc=0x60286b38: bus=0,device=1,function=0,reg=0x04 Mar 09 09:28:10.708 CPU0: PCI: write request (data=0x0000f810) for device 'ti2050b' at pc=0x60286b2c: bus=0,device=1,function=0,reg=0x0c Mar 09 09:28:10.708 CPU0: PCI: write request (data=0x0000f810) for device 'ti2050b' at pc=0x60286b38: bus=0,device=1,function=0,reg=0x0c Mar 09 09:28:10.708 CPU0: PCI: write request (data=0x00040100) for device 'ti2050b' at pc=0x60286b2c: bus=0,device=1,function=0,reg=0x18 Mar 09 09:28:10.708 PCI: PCI bridge 0,1,0 -> pri: 00, sec: 01, sub: 04 Mar 09 09:28:10.708 CPU0: PCI: write request (data=0x00040100) for device 'ti2050b' at pc=0x60286b38: bus=0,device=1,function=0,reg=0x18 Mar 09 09:28:10.708 PCI: PCI bridge 0,1,0 -> pri: 00, sec: 01, sub: 04 Mar 09 09:28:10.708 CPU0: PCI: write request (data=0x02801f00) for device 'ti2050b' at pc=0x60286b2c: bus=0,device=1,function=0,reg=0x1c Mar 09 09:28:10.708 CPU0: PCI: write request (data=0x02801f00) for device 'ti2050b' at pc=0x60286b38: bus=0,device=1,function=0,reg=0x1c Mar 09 09:28:10.708 CPU0: PCI: write request (data=0x4d704d00) for device 'ti2050b' at pc=0x60286b2c: bus=0,device=1,function=0,reg=0x20 Mar 09 09:28:10.708 CPU0: PCI: write request (data=0x4d704d00) for device 'ti2050b' at pc=0x60286b38: bus=0,device=1,function=0,reg=0x20 Mar 09 09:28:10.708 CPU0: PCI: write request (data=0x00014d01) for device 'ti2050b' at pc=0x60286b2c: bus=0,device=1,function=0,reg=0x24 Mar 09 09:28:10.708 CPU0: PCI: write request (data=0x00014d01) for device 'ti2050b' at pc=0x60286b38: bus=0,device=1,function=0,reg=0x24 Mar 09 09:28:10.708 CPU0: PCI: write request (data=0x00200020) for device 'ti2050b' at pc=0x60286b2c: bus=0,device=1,function=0,reg=0x30 Mar 09 09:28:10.708 CPU0: PCI: write request (data=0x00200020) for device 'ti2050b' at pc=0x60286b38: bus=0,device=1,function=0,reg=0x30 Mar 09 09:28:10.708 CPU0: PCI: write request (data=0x03000000) for device 'ti2050b' at pc=0x60286b2c: bus=0,device=1,function=0,reg=0x3c Mar 09 09:28:10.708 CPU0: PCI: write request (data=0x03000000) for device 'ti2050b' at pc=0x60286b38: bus=0,device=1,function=0,reg=0x3c Mar 09 09:28:10.708 CPU0: PCI: write request (data=0x00000000) for device 'ti2050b' at pc=0x60286b2c: bus=0,device=1,function=0,reg=0x40 Mar 09 09:28:10.708 CPU0: PCI: write request (data=0x00000000) for device 'ti2050b' at pc=0x60286b38: bus=0,device=1,function=0,reg=0x40 Mar 09 09:28:10.708 CPU0: PCI: write request (data=0x00000000) for device 'ti2050b' at pc=0x60286b2c: bus=0,device=1,function=0,reg=0x64 Mar 09 09:28:10.708 CPU0: PCI: write request (data=0x00000000) for device 'ti2050b' at pc=0x60286b38: bus=0,device=1,function=0,reg=0x64 Mar 09 09:28:10.708 CPU0: PCI: write request (data=0x00000000) for device 'ti2050b' at pc=0x60286b2c: bus=0,device=1,function=0,reg=0x68 Mar 09 09:28:10.708 CPU0: PCI: write request (data=0x00000000) for device 'ti2050b' at pc=0x60286b38: bus=0,device=1,function=0,reg=0x68 Mar 09 09:28:10.708 CPU0: PCI: write request (data=0x00000007) for device 'ti2050b' at pc=0x60286b2c: bus=0,device=1,function=0,reg=0x04 Mar 09 09:28:10.708 CPU0: PCI: write request (data=0x00000007) for device 'ti2050b' at pc=0x60286b38: bus=0,device=1,function=0,reg=0x04 Mar 09 09:28:10.708 CPU0: PCI: write request (data=0x00000001) for device 'ti2050b' at pc=0x60286b2c: bus=0,device=1,function=0,reg=0xf0 Mar 09 09:28:10.708 CPU0: PCI: write request (data=0x00000001) for device 'ti2050b' at pc=0x60286b38: bus=0,device=1,function=0,reg=0xf0 Mar 09 09:28:10.965 CPU0: JIT: partial JIT flush (count=175) Mar 09 09:28:11.118 CPU0: MTS: read access to undefined address 0x3c080004 at pc=0x60678648 (size=1) Mar 09 09:28:11.118 CPU0: MTS: write access to undefined address 0x3c080004 at pc=0x60678650, value=0x00000004 (size=1) Mar 09 09:28:11.121 CPU0: MTS: read access to undefined address 0x3c080001 at pc=0x6069ce5c (size=1) Mar 09 09:28:11.121 CPU0: MTS: write access to undefined address 0x3c080001 at pc=0x6069ce80, value=0x00000008 (size=1) Mar 09 09:28:11.121 CPU0: MTS: read access to undefined address 0x3c080004 at pc=0x6069cea0 (size=1) Mar 09 09:28:11.121 CPU0: MTS: write access to undefined address 0x3c080004 at pc=0x6069cea8, value=0x00000002 (size=1) Mar 09 09:28:11.121 CPU0: MTS: read access to undefined address 0x3c080004 at pc=0x6069cebc (size=1) Mar 09 09:28:11.121 CPU0: MTS: write access to undefined address 0x3c080004 at pc=0x6069cef8, value=0x00000000 (size=1) Mar 09 09:28:11.123 CPU0: MTS: read access to undefined address 0x3c080025 at pc=0x60676ae0 (size=1) Mar 09 09:28:11.123 CPU0: MTS: write access to undefined address 0x3c080025 at pc=0x60676aec, value=0x00000000 (size=1) Mar 09 09:28:11.123 CPU0: MTS: read access to undefined address 0x3c080026 at pc=0x60676bf0 (size=1) Mar 09 09:28:11.123 CPU0: MTS: write access to undefined address 0x3c080026 at pc=0x60676e20, value=0x00000002 (size=1) Mar 09 09:28:11.123 CPU0: MTS: read access to undefined address 0x3c08001f at pc=0x60676f6c (size=1) Mar 09 09:28:11.123 CPU0: MTS: write access to undefined address 0x3c08001f at pc=0x60676f78, value=0x00000000 (size=1) Mar 09 09:28:11.123 CPU0: MTS: read access to undefined address 0x3c080001 at pc=0x6069cc18 (size=1) Mar 09 09:28:11.123 CPU0: MTS: write access to undefined address 0x3c080001 at pc=0x6069cc20, value=0x00000000 (size=1) Mar 09 09:28:11.123 CPU0: MTS: read access to undefined address 0x3c080001 at pc=0x6069cc40 (size=1) Mar 09 09:28:11.123 CPU0: MTS: write access to undefined address 0x3c080001 at pc=0x6069cc48, value=0x00000000 (size=1) Mar 09 09:28:11.123 CPU0: MTS: read access to undefined address 0x3c080001 at pc=0x6069cc5c (size=1) Mar 09 09:28:11.123 CPU0: MTS: write access to undefined address 0x3c080001 at pc=0x6069cce8, value=0x00000004 (size=1) Mar 09 09:28:11.123 CPU0: MTS: read access to undefined address 0x3c08001f at pc=0x6067697c (size=1) Mar 09 09:28:11.127 CPU0: PCI: read request for device 'NM-1FE-TX(1)' at pc=0x60286c60: bus=1,device=0,function=0,reg=0x00 Mar 09 09:28:11.127 CPU0: PCI: read request for device 'NM-1FE-TX(1)' at pc=0x60286c64: bus=1,device=0,function=0,reg=0x00 Mar 09 09:28:11.127 CPU0: PCI: read request for device 'NM-1FE-TX(1)' at pc=0x60286c60: bus=1,device=0,function=0,reg=0x00 Mar 09 09:28:11.127 CPU0: PCI: read request for device 'NM-1FE-TX(1)' at pc=0x60286c64: bus=1,device=0,function=0,reg=0x00 Mar 09 09:28:11.127 CPU0: PCI: write request (data=0x4d000000) for device 'NM-1FE-TX(1)' at pc=0x60286b2c: bus=1,device=0,function=0,reg=0x14 Mar 09 09:28:11.127 NM-1FE-TX(1): registers are mapped at 0x4d000000 Mar 09 09:28:11.127 CPU0: PCI: write request (data=0x4d000000) for device 'NM-1FE-TX(1)' at pc=0x60286b38: bus=1,device=0,function=0,reg=0x14 Mar 09 09:28:11.127 NM-1FE-TX(1): registers are mapped at 0x4d000000 Mar 09 09:28:11.127 CPU0: PCI: write request (data=0x00000006) for device 'NM-1FE-TX(1)' at pc=0x60286b2c: bus=1,device=0,function=0,reg=0x04 Mar 09 09:28:11.127 CPU0: PCI: write request (data=0x00000006) for device 'NM-1FE-TX(1)' at pc=0x60286b38: bus=1,device=0,function=0,reg=0x04 Mar 09 09:28:11.127 CPU0: PCI: write request (data=0x00004000) for device 'NM-1FE-TX(1)' at pc=0x60286b2c: bus=1,device=0,function=0,reg=0x0c Mar 09 09:28:11.127 CPU0: PCI: write request (data=0x00004000) for device 'NM-1FE-TX(1)' at pc=0x60286b38: bus=1,device=0,function=0,reg=0x0c Mar 09 09:28:11.127 CPU0: PCI: read request for device 'NM-1FE-TX(1)' at pc=0x60286c60: bus=1,device=0,function=0,reg=0x00 Mar 09 09:28:11.127 CPU0: PCI: read request for device 'NM-1FE-TX(1)' at pc=0x60286c64: bus=1,device=0,function=0,reg=0x00 Mar 09 09:28:11.128 CPU0: PCI: write request (data=0x00004000) for device 'NM-1FE-TX(1)' at pc=0x60286b2c: bus=1,device=0,function=0,reg=0x0c Mar 09 09:28:11.128 CPU0: PCI: write request (data=0x00004000) for device 'NM-1FE-TX(1)' at pc=0x60286b38: bus=1,device=0,function=0,reg=0x0c Mar 09 09:28:11.158 NM-1FE-TX(1): fetching init block at address 0x0f7e43a0 Mar 09 09:28:11.158 NM-1FE-TX(1): rx_ring = 0x0f7e4400 (64), tx_ring = 0x0f7e4840 (128) Mar 09 09:28:11.158 NM-1FE-TX(1): CSR0 = 0x0101 Mar 09 09:28:11.202 CPU0: JIT: flushing data structures (compiled pages=277) Mar 09 09:28:11.218 CPU0: IO_FPGA: read from unknown addr 0x4c, pc=0x60277d00 (size=2) Mar 09 09:28:11.218 CPU0: IO_FPGA: write to unknown addr 0x4c, value=0x0, pc=0x60277d08 (size=2) Mar 09 09:28:11.218 CPU0: IO_FPGA: read from unknown addr 0x2e, pc=0x60277d28 (size=2) Mar 09 09:28:11.218 CPU0: IO_FPGA: write to unknown addr 0x2e, value=0x40, pc=0x60277d38 (size=2) Mar 09 09:28:11.224 CPU0: MTS: read access to undefined address 0x3c080001 at pc=0x6069ccb0 (size=1) Mar 09 09:28:11.224 CPU0: MTS: write access to undefined address 0x3c080001 at pc=0x6069cce8, value=0x00000000 (size=1) Mar 09 09:28:11.224 CPU0: MTS: read access to undefined address 0x3c080025 at pc=0x60676ae0 (size=1) Mar 09 09:28:11.224 CPU0: MTS: write access to undefined address 0x3c080025 at pc=0x60676aec, value=0x00000000 (size=1) Mar 09 09:28:11.224 CPU0: MTS: read access to undefined address 0x3c080026 at pc=0x60676e14 (size=1) Mar 09 09:28:11.224 CPU0: MTS: write access to undefined address 0x3c080026 at pc=0x60676e20, value=0x00000000 (size=1) Mar 09 09:28:11.225 CPU0: MTS: read access to undefined address 0x3c08001f at pc=0x60677028 (size=1) Mar 09 09:28:11.225 CPU0: MTS: write access to undefined address 0x3c08001f at pc=0x60676f78, value=0x00000010 (size=1) Mar 09 09:28:11.226 CPU0: MTS: read access to undefined address 0x3c080001 at pc=0x6069ce5c (size=1) Mar 09 09:28:11.226 CPU0: MTS: write access to undefined address 0x3c080001 at pc=0x6069ce80, value=0x00000008 (size=1) Mar 09 09:28:11.226 CPU0: MTS: read access to undefined address 0x3c080004 at pc=0x6069cea0 (size=1) Mar 09 09:28:11.226 CPU0: MTS: write access to undefined address 0x3c080004 at pc=0x6069cea8, value=0x00000002 (size=1) Mar 09 09:28:11.226 CPU0: MTS: read access to undefined address 0x3c080004 at pc=0x6069cebc (size=1) Mar 09 09:28:11.226 CPU0: MTS: write access to undefined address 0x3c080004 at pc=0x6069cef8, value=0x00000000 (size=1) Mar 09 09:28:11.228 CPU0: MTS: read access to undefined address 0x3c080025 at pc=0x60676ae0 (size=1) Mar 09 09:28:11.228 CPU0: MTS: write access to undefined address 0x3c080025 at pc=0x60676aec, value=0x00000000 (size=1) Mar 09 09:28:11.228 CPU0: MTS: read access to undefined address 0x3c080026 at pc=0x60676bf0 (size=1) Mar 09 09:28:11.228 CPU0: MTS: write access to undefined address 0x3c080026 at pc=0x60676e20, value=0x00000002 (size=1) Mar 09 09:28:11.229 CPU0: MTS: read access to undefined address 0x3c08001f at pc=0x60676f6c (size=1) Mar 09 09:28:11.229 CPU0: MTS: write access to undefined address 0x3c08001f at pc=0x60676f78, value=0x00000000 (size=1) Mar 09 09:28:11.229 CPU0: MTS: read access to undefined address 0x3c080001 at pc=0x6069cc18 (size=1) Mar 09 09:28:11.229 CPU0: MTS: write access to undefined address 0x3c080001 at pc=0x6069cc20, value=0x00000000 (size=1) Mar 09 09:28:11.229 CPU0: MTS: read access to undefined address 0x3c080001 at pc=0x6069cc40 (size=1) Mar 09 09:28:11.229 CPU0: MTS: write access to undefined address 0x3c080001 at pc=0x6069cc48, value=0x00000000 (size=1) Mar 09 09:28:11.229 CPU0: MTS: read access to undefined address 0x3c080001 at pc=0x6069cc5c (size=1) Mar 09 09:28:11.229 CPU0: MTS: write access to undefined address 0x3c080001 at pc=0x6069cce8, value=0x00000004 (size=1) Mar 09 09:28:11.229 CPU0: MTS: read access to undefined address 0x3c08001f at pc=0x6067697c (size=1) Mar 09 09:28:11.246 NM-1FE-TX(1): fetching init block at address 0x0f7e43a0 Mar 09 09:28:11.246 NM-1FE-TX(1): rx_ring = 0x0f7e4400 (64), tx_ring = 0x0f7e4840 (128) Mar 09 09:28:11.246 NM-1FE-TX(1): CSR0 = 0x0101 Mar 09 09:28:11.273 CPU0: JIT: partial JIT flush (count=199) Mar 09 09:28:11.336 CPU0: JIT: flushing data structures (compiled pages=281) Mar 09 09:28:11.413 CPU0: JIT: partial JIT flush (count=200) Mar 09 09:28:11.460 CPU0: MTS: read access to undefined address 0x3c080001 at pc=0x6069ccb0 (size=1) Mar 09 09:28:11.460 CPU0: MTS: write access to undefined address 0x3c080001 at pc=0x6069cce8, value=0x00000000 (size=1) Mar 09 09:28:11.460 CPU0: MTS: read access to undefined address 0x3c080025 at pc=0x60676ae0 (size=1) Mar 09 09:28:11.460 CPU0: MTS: write access to undefined address 0x3c080025 at pc=0x60676aec, value=0x00000000 (size=1) Mar 09 09:28:11.460 CPU0: MTS: read access to undefined address 0x3c080026 at pc=0x60676e14 (size=1) Mar 09 09:28:11.460 CPU0: MTS: write access to undefined address 0x3c080026 at pc=0x60676e20, value=0x00000000 (size=1) Mar 09 09:28:11.461 CPU0: MTS: read access to undefined address 0x3c08001f at pc=0x60677028 (size=1) Mar 09 09:28:11.461 CPU0: MTS: write access to undefined address 0x3c08001f at pc=0x60676f78, value=0x00000010 (size=1) Mar 09 09:28:11.463 CPU0: MTS: read access to undefined address 0x3c080001 at pc=0x6069ce5c (size=1) Mar 09 09:28:11.463 CPU0: MTS: write access to undefined address 0x3c080001 at pc=0x6069ce80, value=0x00000008 (size=1) Mar 09 09:28:11.463 CPU0: MTS: read access to undefined address 0x3c080004 at pc=0x6069cea0 (size=1) Mar 09 09:28:11.463 CPU0: MTS: write access to undefined address 0x3c080004 at pc=0x6069cea8, value=0x00000002 (size=1) Mar 09 09:28:11.463 CPU0: MTS: read access to undefined address 0x3c080004 at pc=0x6069cebc (size=1) Mar 09 09:28:11.463 CPU0: MTS: write access to undefined address 0x3c080004 at pc=0x6069cef8, value=0x00000000 (size=1) Mar 09 09:28:11.465 CPU0: MTS: read access to undefined address 0x3c080025 at pc=0x60676ae0 (size=1) Mar 09 09:28:11.465 CPU0: MTS: write access to undefined address 0x3c080025 at pc=0x60676aec, value=0x00000000 (size=1) Mar 09 09:28:11.465 CPU0: MTS: read access to undefined address 0x3c080026 at pc=0x60676bf0 (size=1) Mar 09 09:28:11.465 CPU0: MTS: write access to undefined address 0x3c080026 at pc=0x60676e20, value=0x00000002 (size=1) Mar 09 09:28:11.465 CPU0: MTS: read access to undefined address 0x3c08001f at pc=0x60676f6c (size=1) Mar 09 09:28:11.465 CPU0: MTS: write access to undefined address 0x3c08001f at pc=0x60676f78, value=0x00000000 (size=1) Mar 09 09:28:11.465 CPU0: MTS: read access to undefined address 0x3c080001 at pc=0x6069cc18 (size=1) Mar 09 09:28:11.465 CPU0: MTS: write access to undefined address 0x3c080001 at pc=0x6069cc20, value=0x00000000 (size=1) Mar 09 09:28:11.465 CPU0: MTS: read access to undefined address 0x3c080001 at pc=0x6069cc40 (size=1) Mar 09 09:28:11.465 CPU0: MTS: write access to undefined address 0x3c080001 at pc=0x6069cc48, value=0x00000000 (size=1) Mar 09 09:28:11.465 CPU0: MTS: read access to undefined address 0x3c080001 at pc=0x6069cc5c (size=1) Mar 09 09:28:11.465 CPU0: MTS: write access to undefined address 0x3c080001 at pc=0x6069cce8, value=0x00000004 (size=1) Mar 09 09:28:11.465 CPU0: MTS: read access to undefined address 0x3c08001f at pc=0x6067697c (size=1) Mar 09 09:28:11.487 NM-1FE-TX(1): fetching init block at address 0x0f7e43a0 Mar 09 09:28:11.487 NM-1FE-TX(1): rx_ring = 0x0f7e4400 (64), tx_ring = 0x0f7e4840 (128) Mar 09 09:28:11.487 NM-1FE-TX(1): CSR0 = 0x0101 Mar 09 09:28:11.501 CPU0: MTS: read access to undefined address 0x3c080001 at pc=0x6069ccb0 (size=1) Mar 09 09:28:11.501 CPU0: MTS: write access to undefined address 0x3c080001 at pc=0x6069cce8, value=0x00000000 (size=1) Mar 09 09:28:11.501 CPU0: MTS: read access to undefined address 0x3c080025 at pc=0x60676ae0 (size=1) Mar 09 09:28:11.501 CPU0: MTS: write access to undefined address 0x3c080025 at pc=0x60676aec, value=0x00000000 (size=1) Mar 09 09:28:11.501 CPU0: MTS: read access to undefined address 0x3c080026 at pc=0x60676e14 (size=1) Mar 09 09:28:11.501 CPU0: MTS: write access to undefined address 0x3c080026 at pc=0x60676e20, value=0x00000000 (size=1) Mar 09 09:28:11.501 CPU0: MTS: read access to undefined address 0x3c08001f at pc=0x60677028 (size=1) Mar 09 09:28:11.501 CPU0: MTS: write access to undefined address 0x3c08001f at pc=0x60676f78, value=0x00000010 (size=1) Mar 09 09:28:11.502 CPU0: MTS: read access to undefined address 0x3c080001 at pc=0x6069ce5c (size=1) Mar 09 09:28:11.502 CPU0: MTS: write access to undefined address 0x3c080001 at pc=0x6069ce80, value=0x00000008 (size=1) Mar 09 09:28:11.502 CPU0: MTS: read access to undefined address 0x3c080004 at pc=0x6069cea0 (size=1) Mar 09 09:28:11.502 CPU0: MTS: write access to undefined address 0x3c080004 at pc=0x6069cea8, value=0x00000002 (size=1) Mar 09 09:28:11.502 CPU0: MTS: read access to undefined address 0x3c080004 at pc=0x6069cebc (size=1) Mar 09 09:28:11.502 CPU0: MTS: write access to undefined address 0x3c080004 at pc=0x6069cef8, value=0x00000000 (size=1) Mar 09 09:28:11.502 CPU0: MTS: read access to undefined address 0x3c080025 at pc=0x60676ae0 (size=1) Mar 09 09:28:11.502 CPU0: MTS: write access to undefined address 0x3c080025 at pc=0x60676aec, value=0x00000000 (size=1) Mar 09 09:28:11.502 CPU0: MTS: read access to undefined address 0x3c080026 at pc=0x60676bf0 (size=1) Mar 09 09:28:11.502 CPU0: MTS: write access to undefined address 0x3c080026 at pc=0x60676e20, value=0x00000002 (size=1) Mar 09 09:28:11.502 CPU0: MTS: read access to undefined address 0x3c08001f at pc=0x60676f6c (size=1) Mar 09 09:28:11.502 CPU0: MTS: write access to undefined address 0x3c08001f at pc=0x60676f78, value=0x00000000 (size=1) Mar 09 09:28:11.502 CPU0: MTS: read access to undefined address 0x3c080001 at pc=0x6069cc18 (size=1) Mar 09 09:28:11.502 CPU0: MTS: write access to undefined address 0x3c080001 at pc=0x6069cc20, value=0x00000000 (size=1) Mar 09 09:28:11.502 CPU0: MTS: read access to undefined address 0x3c080001 at pc=0x6069cc40 (size=1) Mar 09 09:28:11.502 CPU0: MTS: write access to undefined address 0x3c080001 at pc=0x6069cc48, value=0x00000000 (size=1) Mar 09 09:28:11.502 CPU0: MTS: read access to undefined address 0x3c080001 at pc=0x6069cc5c (size=1) Mar 09 09:28:11.502 CPU0: MTS: write access to undefined address 0x3c080001 at pc=0x6069cce8, value=0x00000004 (size=1) Mar 09 09:28:11.502 CPU0: MTS: read access to undefined address 0x3c08001f at pc=0x6067697c (size=1) Mar 09 09:28:11.504 NM-1FE-TX(1): fetching init block at address 0x0f7e43a0 Mar 09 09:28:11.504 NM-1FE-TX(1): rx_ring = 0x0f7e4400 (64), tx_ring = 0x0f7e4840 (128) Mar 09 09:28:11.504 NM-1FE-TX(1): CSR0 = 0x0101 Mar 09 09:28:11.507 CPU0: MTS: read access to undefined address 0x3c080001 at pc=0x6069ccb0 (size=1) Mar 09 09:28:11.507 CPU0: MTS: write access to undefined address 0x3c080001 at pc=0x6069cce8, value=0x00000000 (size=1) Mar 09 09:28:11.507 CPU0: MTS: read access to undefined address 0x3c080025 at pc=0x60676ae0 (size=1) Mar 09 09:28:11.507 CPU0: MTS: write access to undefined address 0x3c080025 at pc=0x60676aec, value=0x00000000 (size=1) Mar 09 09:28:11.507 CPU0: MTS: read access to undefined address 0x3c080026 at pc=0x60676e14 (size=1) Mar 09 09:28:11.507 CPU0: MTS: write access to undefined address 0x3c080026 at pc=0x60676e20, value=0x00000000 (size=1) Mar 09 09:28:11.507 CPU0: MTS: read access to undefined address 0x3c08001f at pc=0x60677028 (size=1) Mar 09 09:28:11.507 CPU0: MTS: write access to undefined address 0x3c08001f at pc=0x60676f78, value=0x00000010 (size=1) Mar 09 09:28:11.507 CPU0: MTS: read access to undefined address 0x3c080001 at pc=0x6069ce5c (size=1) Mar 09 09:28:11.507 CPU0: MTS: write access to undefined address 0x3c080001 at pc=0x6069ce80, value=0x00000008 (size=1) Mar 09 09:28:11.507 CPU0: MTS: read access to undefined address 0x3c080004 at pc=0x6069cea0 (size=1) Mar 09 09:28:11.507 CPU0: MTS: write access to undefined address 0x3c080004 at pc=0x6069cea8, value=0x00000002 (size=1) Mar 09 09:28:11.507 CPU0: MTS: read access to undefined address 0x3c080004 at pc=0x6069cebc (size=1) Mar 09 09:28:11.507 CPU0: MTS: write access to undefined address 0x3c080004 at pc=0x6069cef8, value=0x00000000 (size=1) Mar 09 09:28:11.507 CPU0: MTS: read access to undefined address 0x3c080025 at pc=0x60676ae0 (size=1) Mar 09 09:28:11.507 CPU0: MTS: write access to undefined address 0x3c080025 at pc=0x60676aec, value=0x00000000 (size=1) Mar 09 09:28:11.507 CPU0: MTS: read access to undefined address 0x3c080026 at pc=0x60676bf0 (size=1) Mar 09 09:28:11.507 CPU0: MTS: write access to undefined address 0x3c080026 at pc=0x60676e20, value=0x00000002 (size=1) Mar 09 09:28:11.507 CPU0: MTS: read access to undefined address 0x3c08001f at pc=0x60676f6c (size=1) Mar 09 09:28:11.507 CPU0: MTS: write access to undefined address 0x3c08001f at pc=0x60676f78, value=0x00000000 (size=1) Mar 09 09:28:11.507 CPU0: MTS: read access to undefined address 0x3c080001 at pc=0x6069cc18 (size=1) Mar 09 09:28:11.507 CPU0: MTS: write access to undefined address 0x3c080001 at pc=0x6069cc20, value=0x00000000 (size=1) Mar 09 09:28:11.507 CPU0: MTS: read access to undefined address 0x3c080001 at pc=0x6069cc40 (size=1) Mar 09 09:28:11.507 CPU0: MTS: write access to undefined address 0x3c080001 at pc=0x6069cc48, value=0x00000000 (size=1) Mar 09 09:28:11.507 CPU0: MTS: read access to undefined address 0x3c080001 at pc=0x6069cc5c (size=1) Mar 09 09:28:11.507 CPU0: MTS: write access to undefined address 0x3c080001 at pc=0x6069cce8, value=0x00000004 (size=1) Mar 09 09:28:11.507 CPU0: MTS: read access to undefined address 0x3c08001f at pc=0x6067697c (size=1) Mar 09 09:28:11.509 NM-1FE-TX(1): fetching init block at address 0x0f7e43a0 Mar 09 09:28:11.509 NM-1FE-TX(1): rx_ring = 0x0f7e4400 (64), tx_ring = 0x0f7e4840 (128) Mar 09 09:28:11.509 NM-1FE-TX(1): CSR0 = 0x0101 Mar 09 09:28:11.513 CPU0: JIT: flushing data structures (compiled pages=308) Mar 09 09:28:11.622 CPU0: JIT: partial JIT flush (count=201) Mar 09 09:28:11.668 CPU0: MTS: read access to undefined address 0x3c080001 at pc=0x6069ccb0 (size=1) Mar 09 09:28:11.668 CPU0: MTS: write access to undefined address 0x3c080001 at pc=0x6069cce8, value=0x00000000 (size=1) Mar 09 09:28:11.669 CPU0: MTS: read access to undefined address 0x3c080025 at pc=0x60676ae0 (size=1) Mar 09 09:28:11.669 CPU0: MTS: write access to undefined address 0x3c080025 at pc=0x60676aec, value=0x00000000 (size=1) Mar 09 09:28:11.669 CPU0: MTS: read access to undefined address 0x3c080026 at pc=0x60676e14 (size=1) Mar 09 09:28:11.669 CPU0: MTS: write access to undefined address 0x3c080026 at pc=0x60676e20, value=0x00000000 (size=1) Mar 09 09:28:11.669 CPU0: MTS: read access to undefined address 0x3c08001f at pc=0x60677028 (size=1) Mar 09 09:28:11.669 CPU0: MTS: write access to undefined address 0x3c08001f at pc=0x60676f78, value=0x00000010 (size=1) Mar 09 09:28:11.671 CPU0: MTS: read access to undefined address 0x3c080001 at pc=0x6069ce5c (size=1) Mar 09 09:28:11.671 CPU0: MTS: write access to undefined address 0x3c080001 at pc=0x6069ce80, value=0x00000008 (size=1) Mar 09 09:28:11.671 CPU0: MTS: read access to undefined address 0x3c080004 at pc=0x6069cea0 (size=1) Mar 09 09:28:11.671 CPU0: MTS: write access to undefined address 0x3c080004 at pc=0x6069cea8, value=0x00000002 (size=1) Mar 09 09:28:11.671 CPU0: MTS: read access to undefined address 0x3c080004 at pc=0x6069cebc (size=1) Mar 09 09:28:11.671 CPU0: MTS: write access to undefined address 0x3c080004 at pc=0x6069cef8, value=0x00000000 (size=1) Mar 09 09:28:11.673 CPU0: MTS: read access to undefined address 0x3c080025 at pc=0x60676ae0 (size=1) Mar 09 09:28:11.673 CPU0: MTS: write access to undefined address 0x3c080025 at pc=0x60676aec, value=0x00000000 (size=1) Mar 09 09:28:11.673 CPU0: MTS: read access to undefined address 0x3c080026 at pc=0x60676bf0 (size=1) Mar 09 09:28:11.673 CPU0: MTS: write access to undefined address 0x3c080026 at pc=0x60676e20, value=0x00000002 (size=1) Mar 09 09:28:11.673 CPU0: MTS: read access to undefined address 0x3c08001f at pc=0x60676f6c (size=1) Mar 09 09:28:11.673 CPU0: MTS: write access to undefined address 0x3c08001f at pc=0x60676f78, value=0x00000000 (size=1) Mar 09 09:28:11.673 CPU0: MTS: read access to undefined address 0x3c080001 at pc=0x6069cc18 (size=1) Mar 09 09:28:11.673 CPU0: MTS: write access to undefined address 0x3c080001 at pc=0x6069cc20, value=0x00000000 (size=1) Mar 09 09:28:11.673 CPU0: MTS: read access to undefined address 0x3c080001 at pc=0x6069cc40 (size=1) Mar 09 09:28:11.673 CPU0: MTS: write access to undefined address 0x3c080001 at pc=0x6069cc48, value=0x00000000 (size=1) Mar 09 09:28:11.673 CPU0: MTS: read access to undefined address 0x3c080001 at pc=0x6069cc5c (size=1) Mar 09 09:28:11.673 CPU0: MTS: write access to undefined address 0x3c080001 at pc=0x6069cce8, value=0x00000004 (size=1) Mar 09 09:28:11.673 CPU0: MTS: read access to undefined address 0x3c08001f at pc=0x6067697c (size=1) Mar 09 09:28:11.677 NM-1FE-TX(1): fetching init block at address 0x0f7e43a0 Mar 09 09:28:11.677 NM-1FE-TX(1): rx_ring = 0x0f7e4400 (64), tx_ring = 0x0f7e4840 (128) Mar 09 09:28:11.677 NM-1FE-TX(1): CSR0 = 0x0101 Mar 09 09:28:11.686 CPU0: JIT: flushing data structures (compiled pages=311) Mar 09 09:28:11.996 CPU0: JIT: partial JIT flush (count=165) Mar 09 09:28:12.045 CPU0: JIT: flushing data structures (compiled pages=308) Mar 09 09:28:12.119 CPU0: JIT: partial JIT flush (count=199) Mar 09 09:28:12.194 CPU0: JIT: flushing data structures (compiled pages=310) Mar 09 09:28:12.289 CPU0: JIT: partial JIT flush (count=202) Mar 09 09:28:12.437 CPU0: JIT: flushing data structures (compiled pages=318) Mar 09 09:28:12.499 CPU0: JIT: partial JIT flush (count=199) Mar 09 09:28:12.563 CPU0: JIT: flushing data structures (compiled pages=318) Mar 09 09:28:12.652 CPU0: JIT: partial JIT flush (count=189) Mar 09 09:28:12.742 CPU0: JIT: flushing data structures (compiled pages=327) Mar 09 09:28:12.853 CPU0: JIT: partial JIT flush (count=165) Mar 09 09:28:13.111 CPU0: JIT: flushing data structures (compiled pages=559) Mar 09 09:28:13.181 CPU0: JIT: partial JIT flush (count=189) Mar 09 09:28:13.728 CPU0: JIT: flushing data structures (compiled pages=555) Mar 09 09:28:13.772 ROM: trying to read bootvar 'PMDEBUG' Mar 09 09:28:13.786 ROM: trying to read bootvar 'MONDEBUG' Mar 09 09:28:13.856 CPU0: JIT: partial JIT flush (count=199) Mar 09 09:28:14.260 CPU0: JIT: flushing data structures (compiled pages=562) Mar 09 09:28:14.541 CPU0: JIT: partial JIT flush (count=193) Mar 09 09:28:14.679 CPU0: JIT: flushing data structures (compiled pages=562) Mar 09 09:28:14.742 CPU0: JIT: partial JIT flush (count=213) Mar 09 09:28:14.773 ROM: unhandled syscall 0x0000001a at pc=0x60a9e9bc (a1=0x65024a6c,a2=0x00000001,a3=0x00000023) Mar 09 09:28:14.773 ROM: unhandled syscall 0x00000009 at pc=0x60a9e9bc (a1=0x65024a6c,a2=0x00000001,a3=0x00000023) Mar 09 09:28:14.823 CPU0: JIT: flushing data structures (compiled pages=557) Mar 09 09:28:14.935 CPU0: JIT: partial JIT flush (count=194) Mar 09 09:28:14.990 CPU0: JIT: flushing data structures (compiled pages=564) Mar 09 09:28:15.049 CPU0: JIT: partial JIT flush (count=215) Mar 09 09:28:15.099 CPU0: JIT: flushing data structures (compiled pages=552) Mar 09 09:28:15.156 CPU0: JIT: partial JIT flush (count=213) Mar 09 09:28:15.256 CPU0: JIT: flushing data structures (compiled pages=557) Mar 09 09:28:15.483 CPU0: JIT: partial JIT flush (count=182) Mar 09 09:28:15.564 CPU0: JIT: flushing data structures (compiled pages=558) Mar 09 09:28:15.712 CPU0: JIT: partial JIT flush (count=183) Mar 09 09:28:15.764 CPU0: JIT: flushing data structures (compiled pages=556) Mar 09 09:28:15.834 CPU0: JIT: partial JIT flush (count=210) Mar 09 09:28:15.885 CPU0: JIT: flushing data structures (compiled pages=554) Mar 09 09:28:15.959 CPU0: JIT: partial JIT flush (count=207) Mar 09 09:28:16.012 CPU0: JIT: flushing data structures (compiled pages=559) Mar 09 09:28:16.098 CPU0: JIT: partial JIT flush (count=207) Mar 09 09:28:16.158 CPU0: JIT: flushing data structures (compiled pages=560) Mar 09 09:28:16.209 CPU0: MTS: read access to undefined address 0x3c080001 at pc=0x6069ccb0 (size=1) Mar 09 09:28:16.210 CPU0: MTS: write access to undefined address 0x3c080001 at pc=0x6069cce8, value=0x00000000 (size=1) Mar 09 09:28:16.211 CPU0: MTS: read access to undefined address 0x3c080025 at pc=0x60676ae0 (size=1) Mar 09 09:28:16.211 CPU0: MTS: write access to undefined address 0x3c080025 at pc=0x60676aec, value=0x00000000 (size=1) Mar 09 09:28:16.211 CPU0: MTS: read access to undefined address 0x3c080026 at pc=0x60676e14 (size=1) Mar 09 09:28:16.211 CPU0: MTS: write access to undefined address 0x3c080026 at pc=0x60676e20, value=0x00000000 (size=1) Mar 09 09:28:16.211 CPU0: MTS: read access to undefined address 0x3c08001f at pc=0x60677028 (size=1) Mar 09 09:28:16.211 CPU0: MTS: write access to undefined address 0x3c08001f at pc=0x60676f78, value=0x00000010 (size=1) Mar 09 09:28:16.218 CPU0: MTS: read access to undefined address 0x3c080001 at pc=0x6069ce5c (size=1) Mar 09 09:28:16.218 CPU0: MTS: write access to undefined address 0x3c080001 at pc=0x6069ce80, value=0x00000008 (size=1) Mar 09 09:28:16.218 CPU0: MTS: read access to undefined address 0x3c080004 at pc=0x6069cea0 (size=1) Mar 09 09:28:16.218 CPU0: MTS: write access to undefined address 0x3c080004 at pc=0x6069cea8, value=0x00000002 (size=1) Mar 09 09:28:16.218 CPU0: MTS: read access to undefined address 0x3c080004 at pc=0x6069cebc (size=1) Mar 09 09:28:16.218 CPU0: MTS: write access to undefined address 0x3c080004 at pc=0x6069cef8, value=0x00000000 (size=1) Mar 09 09:28:16.221 CPU0: MTS: read access to undefined address 0x3c080025 at pc=0x60676ae0 (size=1) Mar 09 09:28:16.221 CPU0: MTS: write access to undefined address 0x3c080025 at pc=0x60676aec, value=0x00000000 (size=1) Mar 09 09:28:16.221 CPU0: MTS: read access to undefined address 0x3c080026 at pc=0x60676bf0 (size=1) Mar 09 09:28:16.221 CPU0: MTS: write access to undefined address 0x3c080026 at pc=0x60676e20, value=0x00000002 (size=1) Mar 09 09:28:16.221 CPU0: MTS: read access to undefined address 0x3c08001f at pc=0x60676f6c (size=1) Mar 09 09:28:16.221 CPU0: MTS: write access to undefined address 0x3c08001f at pc=0x60676f78, value=0x00000000 (size=1) Mar 09 09:28:16.221 CPU0: MTS: read access to undefined address 0x3c080001 at pc=0x6069cc18 (size=1) Mar 09 09:28:16.221 CPU0: MTS: write access to undefined address 0x3c080001 at pc=0x6069cc20, value=0x00000000 (size=1) Mar 09 09:28:16.221 CPU0: MTS: read access to undefined address 0x3c080001 at pc=0x6069cc40 (size=1) Mar 09 09:28:16.221 CPU0: MTS: write access to undefined address 0x3c080001 at pc=0x6069cc48, value=0x00000000 (size=1) Mar 09 09:28:16.221 CPU0: MTS: read access to undefined address 0x3c080001 at pc=0x6069cc5c (size=1) Mar 09 09:28:16.221 CPU0: MTS: write access to undefined address 0x3c080001 at pc=0x6069cce8, value=0x00000004 (size=1) Mar 09 09:28:16.221 CPU0: MTS: read access to undefined address 0x3c08001f at pc=0x6067697c (size=1) Mar 09 09:28:16.226 CPU0: JIT: partial JIT flush (count=206) Mar 09 09:28:16.282 CPU0: JIT: flushing data structures (compiled pages=559) Mar 09 09:28:16.357 CPU0: JIT: partial JIT flush (count=204) Mar 09 09:28:16.396 CPU0: MTS: read access to undefined address 0x3c080001 at pc=0x6069ccb0 (size=1) Mar 09 09:28:16.396 CPU0: MTS: write access to undefined address 0x3c080001 at pc=0x6069cce8, value=0x00000000 (size=1) Mar 09 09:28:16.396 CPU0: MTS: read access to undefined address 0x3c080025 at pc=0x60676ae0 (size=1) Mar 09 09:28:16.396 CPU0: MTS: write access to undefined address 0x3c080025 at pc=0x60676aec, value=0x00000000 (size=1) Mar 09 09:28:16.396 CPU0: MTS: read access to undefined address 0x3c080026 at pc=0x60676e14 (size=1) Mar 09 09:28:16.396 CPU0: MTS: write access to undefined address 0x3c080026 at pc=0x60676e20, value=0x00000000 (size=1) Mar 09 09:28:16.397 CPU0: MTS: read access to undefined address 0x3c08001f at pc=0x60677028 (size=1) Mar 09 09:28:16.397 CPU0: MTS: write access to undefined address 0x3c08001f at pc=0x60676f78, value=0x00000010 (size=1) Mar 09 09:28:16.401 CPU0: MTS: read access to undefined address 0x3c080001 at pc=0x6069ce5c (size=1) Mar 09 09:28:16.401 CPU0: MTS: write access to undefined address 0x3c080001 at pc=0x6069ce80, value=0x00000008 (size=1) Mar 09 09:28:16.401 CPU0: MTS: read access to undefined address 0x3c080004 at pc=0x6069cea0 (size=1) Mar 09 09:28:16.401 CPU0: MTS: write access to undefined address 0x3c080004 at pc=0x6069cea8, value=0x00000002 (size=1) Mar 09 09:28:16.401 CPU0: MTS: read access to undefined address 0x3c080004 at pc=0x6069cebc (size=1) Mar 09 09:28:16.401 CPU0: MTS: write access to undefined address 0x3c080004 at pc=0x6069cef8, value=0x00000000 (size=1) Mar 09 09:28:16.403 CPU0: MTS: read access to undefined address 0x3c080025 at pc=0x60676ae0 (size=1) Mar 09 09:28:16.403 CPU0: MTS: write access to undefined address 0x3c080025 at pc=0x60676aec, value=0x00000000 (size=1) Mar 09 09:28:16.403 CPU0: MTS: read access to undefined address 0x3c080026 at pc=0x60676bf0 (size=1) Mar 09 09:28:16.403 CPU0: MTS: write access to undefined address 0x3c080026 at pc=0x60676e20, value=0x00000002 (size=1) Mar 09 09:28:16.403 CPU0: MTS: read access to undefined address 0x3c08001f at pc=0x60676f6c (size=1) Mar 09 09:28:16.403 CPU0: MTS: write access to undefined address 0x3c08001f at pc=0x60676f78, value=0x00000000 (size=1) Mar 09 09:28:16.403 CPU0: MTS: read access to undefined address 0x3c080001 at pc=0x6069cc18 (size=1) Mar 09 09:28:16.403 CPU0: MTS: write access to undefined address 0x3c080001 at pc=0x6069cc20, value=0x00000000 (size=1) Mar 09 09:28:16.403 CPU0: MTS: read access to undefined address 0x3c080001 at pc=0x6069cc40 (size=1) Mar 09 09:28:16.403 CPU0: MTS: write access to undefined address 0x3c080001 at pc=0x6069cc48, value=0x00000000 (size=1) Mar 09 09:28:16.403 CPU0: MTS: read access to undefined address 0x3c080001 at pc=0x6069cc5c (size=1) Mar 09 09:28:16.403 CPU0: MTS: write access to undefined address 0x3c080001 at pc=0x6069cce8, value=0x00000004 (size=1) Mar 09 09:28:16.403 CPU0: MTS: read access to undefined address 0x3c08001f at pc=0x6067697c (size=1) Mar 09 09:28:16.403 CPU0: MTS: read access to undefined address 0x3c080001 at pc=0x6069ccb0 (size=1) Mar 09 09:28:16.403 CPU0: MTS: write access to undefined address 0x3c080001 at pc=0x6069cce8, value=0x00000000 (size=1) Mar 09 09:28:16.403 CPU0: MTS: read access to undefined address 0x3c080025 at pc=0x60676ae0 (size=1) Mar 09 09:28:16.403 CPU0: MTS: write access to undefined address 0x3c080025 at pc=0x60676aec, value=0x00000000 (size=1) Mar 09 09:28:16.403 CPU0: MTS: read access to undefined address 0x3c080026 at pc=0x60676e14 (size=1) Mar 09 09:28:16.403 CPU0: MTS: write access to undefined address 0x3c080026 at pc=0x60676e20, value=0x00000000 (size=1) Mar 09 09:28:16.404 CPU0: MTS: read access to undefined address 0x3c08001f at pc=0x60677028 (size=1) Mar 09 09:28:16.404 CPU0: MTS: write access to undefined address 0x3c08001f at pc=0x60676f78, value=0x00000010 (size=1) Mar 09 09:28:16.404 CPU0: MTS: read access to undefined address 0x3c080001 at pc=0x6069ce5c (size=1) Mar 09 09:28:16.404 CPU0: MTS: write access to undefined address 0x3c080001 at pc=0x6069ce80, value=0x00000008 (size=1) Mar 09 09:28:16.404 CPU0: MTS: read access to undefined address 0x3c080004 at pc=0x6069cea0 (size=1) Mar 09 09:28:16.404 CPU0: MTS: write access to undefined address 0x3c080004 at pc=0x6069cea8, value=0x00000002 (size=1) Mar 09 09:28:16.404 CPU0: MTS: read access to undefined address 0x3c080004 at pc=0x6069cebc (size=1) Mar 09 09:28:16.404 CPU0: MTS: write access to undefined address 0x3c080004 at pc=0x6069cef8, value=0x00000000 (size=1) Mar 09 09:28:16.404 CPU0: MTS: read access to undefined address 0x3c080025 at pc=0x60676ae0 (size=1) Mar 09 09:28:16.404 CPU0: MTS: write access to undefined address 0x3c080025 at pc=0x60676aec, value=0x00000000 (size=1) Mar 09 09:28:16.404 CPU0: MTS: read access to undefined address 0x3c080026 at pc=0x60676bf0 (size=1) Mar 09 09:28:16.404 CPU0: MTS: write access to undefined address 0x3c080026 at pc=0x60676e20, value=0x00000002 (size=1) Mar 09 09:28:16.404 CPU0: MTS: read access to undefined address 0x3c08001f at pc=0x60676f6c (size=1) Mar 09 09:28:16.404 CPU0: MTS: write access to undefined address 0x3c08001f at pc=0x60676f78, value=0x00000000 (size=1) Mar 09 09:28:16.404 CPU0: MTS: read access to undefined address 0x3c080001 at pc=0x6069cc18 (size=1) Mar 09 09:28:16.404 CPU0: MTS: write access to undefined address 0x3c080001 at pc=0x6069cc20, value=0x00000000 (size=1) Mar 09 09:28:16.404 CPU0: MTS: read access to undefined address 0x3c080001 at pc=0x6069cc40 (size=1) Mar 09 09:28:16.404 CPU0: MTS: write access to undefined address 0x3c080001 at pc=0x6069cc48, value=0x00000000 (size=1) Mar 09 09:28:16.404 CPU0: MTS: read access to undefined address 0x3c080001 at pc=0x6069cc5c (size=1) Mar 09 09:28:16.404 CPU0: MTS: write access to undefined address 0x3c080001 at pc=0x6069cce8, value=0x00000004 (size=1) Mar 09 09:28:16.404 CPU0: MTS: read access to undefined address 0x3c08001f at pc=0x6067697c (size=1) Mar 09 09:28:16.426 CPU0: JIT: flushing data structures (compiled pages=558) Mar 09 09:28:16.492 CPU0: JIT: partial JIT flush (count=209) Mar 09 09:28:16.535 CPU0: MTS: read access to undefined address 0x3c080001 at pc=0x6069ccb0 (size=1) Mar 09 09:28:16.535 CPU0: MTS: write access to undefined address 0x3c080001 at pc=0x6069cce8, value=0x00000000 (size=1) Mar 09 09:28:16.536 CPU0: MTS: read access to undefined address 0x3c080025 at pc=0x60676ae0 (size=1) Mar 09 09:28:16.536 CPU0: MTS: write access to undefined address 0x3c080025 at pc=0x60676aec, value=0x00000000 (size=1) Mar 09 09:28:16.536 CPU0: MTS: read access to undefined address 0x3c080026 at pc=0x60676e14 (size=1) Mar 09 09:28:16.536 CPU0: MTS: write access to undefined address 0x3c080026 at pc=0x60676e20, value=0x00000000 (size=1) Mar 09 09:28:16.537 CPU0: MTS: read access to undefined address 0x3c08001f at pc=0x60677028 (size=1) Mar 09 09:28:16.537 CPU0: MTS: write access to undefined address 0x3c08001f at pc=0x60676f78, value=0x00000010 (size=1) Mar 09 09:28:16.540 CPU0: MTS: read access to undefined address 0x3c080001 at pc=0x6069ce5c (size=1) Mar 09 09:28:16.540 CPU0: MTS: write access to undefined address 0x3c080001 at pc=0x6069ce80, value=0x00000008 (size=1) Mar 09 09:28:16.541 CPU0: MTS: read access to undefined address 0x3c080004 at pc=0x6069cea0 (size=1) Mar 09 09:28:16.541 CPU0: MTS: write access to undefined address 0x3c080004 at pc=0x6069cea8, value=0x00000002 (size=1) Mar 09 09:28:16.541 CPU0: MTS: read access to undefined address 0x3c080004 at pc=0x6069cebc (size=1) Mar 09 09:28:16.541 CPU0: MTS: write access to undefined address 0x3c080004 at pc=0x6069cef8, value=0x00000000 (size=1) Mar 09 09:28:16.543 CPU0: MTS: read access to undefined address 0x3c080025 at pc=0x60676ae0 (size=1) Mar 09 09:28:16.543 CPU0: MTS: write access to undefined address 0x3c080025 at pc=0x60676aec, value=0x00000000 (size=1) Mar 09 09:28:16.543 CPU0: MTS: read access to undefined address 0x3c080026 at pc=0x60676bf0 (size=1) Mar 09 09:28:16.543 CPU0: MTS: write access to undefined address 0x3c080026 at pc=0x60676e20, value=0x00000002 (size=1) Mar 09 09:28:16.543 CPU0: MTS: read access to undefined address 0x3c08001f at pc=0x60676f6c (size=1) Mar 09 09:28:16.543 CPU0: MTS: write access to undefined address 0x3c08001f at pc=0x60676f78, value=0x00000000 (size=1) Mar 09 09:28:16.543 CPU0: MTS: read access to undefined address 0x3c080001 at pc=0x6069cc18 (size=1) Mar 09 09:28:16.543 CPU0: MTS: write access to undefined address 0x3c080001 at pc=0x6069cc20, value=0x00000000 (size=1) Mar 09 09:28:16.543 CPU0: MTS: read access to undefined address 0x3c080001 at pc=0x6069cc40 (size=1) Mar 09 09:28:16.543 CPU0: MTS: write access to undefined address 0x3c080001 at pc=0x6069cc48, value=0x00000000 (size=1) Mar 09 09:28:16.543 CPU0: MTS: read access to undefined address 0x3c080001 at pc=0x6069cc5c (size=1) Mar 09 09:28:16.543 CPU0: MTS: write access to undefined address 0x3c080001 at pc=0x6069cce8, value=0x00000004 (size=1) Mar 09 09:28:16.543 CPU0: MTS: read access to undefined address 0x3c08001f at pc=0x6067697c (size=1) Mar 09 09:28:16.548 CPU0: JIT: flushing data structures (compiled pages=566) Mar 09 09:28:16.622 CPU0: JIT: partial JIT flush (count=204) Mar 09 09:28:16.685 CPU0: JIT: flushing data structures (compiled pages=567) Mar 09 09:28:16.748 CPU0: JIT: partial JIT flush (count=211) Mar 09 09:28:16.815 CPU0: JIT: flushing data structures (compiled pages=564) Mar 09 09:28:16.892 CPU0: JIT: partial JIT flush (count=207) Mar 09 09:28:16.941 CPU0: JIT: flushing data structures (compiled pages=562) Mar 09 09:28:16.995 NM-1FE-TX(1): fetching init block at address 0x0f7e43a0 Mar 09 09:28:16.995 NM-1FE-TX(1): rx_ring = 0x0f7e4400 (64), tx_ring = 0x0f7e4840 (128) Mar 09 09:28:16.995 NM-1FE-TX(1): CSR0 = 0x0101 Mar 09 09:28:17.000 CPU0: JIT: partial JIT flush (count=208) Mar 09 09:28:17.051 CPU0: JIT: flushing data structures (compiled pages=558) Mar 09 09:28:17.101 CPU0: JIT: partial JIT flush (count=217) Mar 09 09:28:17.171 CPU0: JIT: flushing data structures (compiled pages=572) Mar 09 09:28:17.246 CPU0: JIT: partial JIT flush (count=195) Mar 09 09:28:17.318 ROM: trying to read bootvar 'RANDOM_NUM' Mar 09 09:28:17.324 CPU0: JIT: flushing data structures (compiled pages=568) Mar 09 09:28:17.555 CPU0: JIT: partial JIT flush (count=184) Mar 09 09:28:17.612 CPU0: IO_FPGA: read from unknown addr 0x16, pc=0x608192f4 (size=2) Mar 09 09:28:17.612 CPU0: IO_FPGA: write to unknown addr 0x16, value=0x1, pc=0x608192fc (size=2) Mar 09 09:28:17.616 CPU0: JIT: flushing data structures (compiled pages=564) Mar 09 09:28:17.644 ROM: trying to read bootvar 'ROM_PERSISTENT_UTC' Mar 09 09:28:17.759 CPU0: JIT: partial JIT flush (count=186) Mar 09 09:28:17.830 CPU0: JIT: flushing data structures (compiled pages=569) Mar 09 09:28:17.892 CPU0: JIT: partial JIT flush (count=207) Mar 09 09:28:17.962 CPU0: JIT: flushing data structures (compiled pages=563) Mar 09 09:28:18.094 CPU0: JIT: partial JIT flush (count=211) Mar 09 09:28:18.149 CPU0: MTS: read access to undefined address 0x3c08002c at pc=0x60819f48 (size=1) Mar 09 09:28:18.208 CPU0: JIT: flushing data structures (compiled pages=567) Mar 09 09:28:18.300 CPU0: JIT: partial JIT flush (count=199) Mar 09 09:28:18.383 CPU0: JIT: flushing data structures (compiled pages=566) Mar 09 09:28:18.553 CPU0: JIT: partial JIT flush (count=217) Mar 09 09:28:18.609 CPU0: JIT: flushing data structures (compiled pages=574) Mar 09 09:28:18.754 CPU0: JIT: partial JIT flush (count=193) Mar 09 09:28:18.814 CPU0: JIT: flushing data structures (compiled pages=570) Mar 09 09:28:18.850 CPU0: MTS: read access to undefined address 0x3c08002c at pc=0x60819f48 (size=1) Mar 09 09:28:18.854 ROM: trying to set bootvar 'BSI=0' Mar 09 09:28:18.887 ROM: trying to read bootvar 'RET_2_RCALTS' Mar 09 09:28:18.887 ROM: trying to set bootvar 'RET_2_RCALTS=' Mar 09 09:28:18.922 CPU0: JIT: partial JIT flush (count=202) Mar 09 09:28:18.986 CPU0: JIT: flushing data structures (compiled pages=572) Mar 09 09:28:19.037 CPU0: JIT: partial JIT flush (count=209) Mar 09 09:28:19.107 CPU0: JIT: flushing data structures (compiled pages=567) Mar 09 09:28:19.155 CPU0: MTS: read access to undefined address 0x3c08002c at pc=0x60819f48 (size=1) Mar 09 09:28:19.177 CPU0: JIT: partial JIT flush (count=195) Mar 09 09:28:19.254 CPU0: JIT: flushing data structures (compiled pages=570) Mar 09 09:28:19.304 CPU0: MTS: read access to undefined address 0x3c08002c at pc=0x60819f48 (size=1) Mar 09 09:28:19.344 CPU0: JIT: partial JIT flush (count=185) Mar 09 09:28:19.535 CPU0: MTS: read access to undefined address 0x3c08002c at pc=0x60819f48 (size=1) Mar 09 09:28:19.706 CPU0: JIT: flushing data structures (compiled pages=567) Mar 09 09:28:19.785 CPU0: MTS: read access to undefined address 0x3c08002c at pc=0x60819f48 (size=1) Mar 09 09:28:19.879 CPU0: JIT: partial JIT flush (count=191) Mar 09 09:28:20.064 CPU0: MTS: read access to undefined address 0x3c08002c at pc=0x60819f48 (size=1) Mar 09 09:28:20.301 CPU0: MTS: read access to undefined address 0x3c08002c at pc=0x60819f48 (size=1) Mar 09 09:28:20.472 CPU0: JIT: flushing data structures (compiled pages=564) Mar 09 09:28:20.542 CPU0: MTS: read access to undefined address 0x3c08002c at pc=0x60819f48 (size=1) Mar 09 09:28:20.787 CPU0: MTS: read access to undefined address 0x3c08002c at pc=0x60819f48 (size=1) Mar 09 09:28:20.820 CPU0: JIT: partial JIT flush (count=176) Mar 09 09:28:20.866 CPU0: JIT: flushing data structures (compiled pages=572) Mar 09 09:28:20.936 CPU0: JIT: partial JIT flush (count=211) Mar 09 09:28:21.010 CPU0: JIT: flushing data structures (compiled pages=566) Mar 09 09:28:21.077 CPU0: JIT: partial JIT flush (count=212) Mar 09 09:28:21.127 CPU0: JIT: flushing data structures (compiled pages=562) Mar 09 09:28:21.179 CPU0: MTS: read access to undefined address 0x3c08002c at pc=0x60819f48 (size=1) Mar 09 09:28:21.305 CPU0: JIT: partial JIT flush (count=184) Mar 09 09:28:21.352 CPU0: MTS: read access to undefined address 0x3c08002c at pc=0x60819f48 (size=1) Mar 09 09:28:21.539 CPU0: MTS: read access to undefined address 0x3c08002c at pc=0x60819f48 (size=1) Mar 09 09:28:21.797 CPU0: MTS: read access to undefined address 0x3c08002c at pc=0x60819f48 (size=1) Mar 09 09:28:21.859 CPU0: JIT: flushing data structures (compiled pages=568) Mar 09 09:28:21.906 CPU0: JIT: partial JIT flush (count=215) Mar 09 09:28:21.953 CPU0: JIT: flushing data structures (compiled pages=568) Mar 09 09:28:22.031 CPU0: MTS: read access to undefined address 0x3c08002c at pc=0x60819f48 (size=1) Mar 09 09:28:22.281 CPU0: MTS: read access to undefined address 0x3c08002c at pc=0x60819f48 (size=1) Mar 09 09:28:22.531 CPU0: MTS: read access to undefined address 0x3c08002c at pc=0x60819f48 (size=1) Mar 09 09:28:22.819 CPU0: MTS: read access to undefined address 0x3c08002c at pc=0x60819f48 (size=1) Mar 09 09:28:22.866 CPU0: JIT: partial JIT flush (count=191) Mar 09 09:28:23.038 CPU0: MTS: read access to undefined address 0x3c08002c at pc=0x60819f48 (size=1) Mar 09 09:28:23.319 CPU0: MTS: read access to undefined address 0x3c08002c at pc=0x60819f48 (size=1) Mar 09 09:28:23.538 CPU0: MTS: read access to undefined address 0x3c08002c at pc=0x60819f48 (size=1) Mar 09 09:28:23.719 CPU0: JIT: flushing data structures (compiled pages=564) Mar 09 09:28:23.798 CPU0: MTS: read access to undefined address 0x3c08002c at pc=0x60819f48 (size=1) Mar 09 09:28:23.923 CPU0: JIT: partial JIT flush (count=198) Mar 09 09:28:24.048 CPU0: MTS: read access to undefined address 0x3c08002c at pc=0x60819f48 (size=1) Mar 09 09:28:24.298 CPU0: MTS: read access to undefined address 0x3c08002c at pc=0x60819f48 (size=1) Mar 09 09:28:24.548 CPU0: MTS: read access to undefined address 0x3c08002c at pc=0x60819f48 (size=1) Mar 09 09:28:24.824 CPU0: MTS: read access to undefined address 0x3c08002c at pc=0x60819f48 (size=1) Mar 09 09:28:25.043 CPU0: MTS: read access to undefined address 0x3c08002c at pc=0x60819f48 (size=1) Mar 09 09:28:25.230 CPU0: JIT: flushing data structures (compiled pages=565) Mar 09 09:28:25.340 CPU0: MTS: read access to undefined address 0x3c08002c at pc=0x60819f48 (size=1) Mar 09 09:28:25.530 CPU0: MTS: read access to undefined address 0x3c08002c at pc=0x60819f48 (size=1) Mar 09 09:28:25.805 CPU0: MTS: read access to undefined address 0x3c08002c at pc=0x60819f48 (size=1) Mar 09 09:28:26.055 CPU0: MTS: read access to undefined address 0x3c08002c at pc=0x60819f48 (size=1) Mar 09 09:28:26.305 CPU0: MTS: read access to undefined address 0x3c08002c at pc=0x60819f48 (size=1) Mar 09 09:28:26.477 CPU0: JIT: partial JIT flush (count=182) Mar 09 09:28:26.555 CPU0: MTS: read access to undefined address 0x3c08002c at pc=0x60819f48 (size=1) Mar 09 09:28:26.805 CPU0: MTS: read access to undefined address 0x3c08002c at pc=0x60819f48 (size=1) Mar 09 09:28:26.993 CPU0: JIT: flushing data structures (compiled pages=564) Mar 09 09:28:27.055 CPU0: MTS: read access to undefined address 0x3c08002c at pc=0x60819f48 (size=1) Mar 09 09:28:27.305 CPU0: MTS: read access to undefined address 0x3c08002c at pc=0x60819f48 (size=1) Mar 09 09:28:27.555 CPU0: MTS: read access to undefined address 0x3c08002c at pc=0x60819f48 (size=1) Mar 09 09:28:27.798 CPU0: MTS: read access to undefined address 0x3c08002c at pc=0x60819f48 (size=1) Mar 09 09:28:28.048 CPU0: MTS: read access to undefined address 0x3c08002c at pc=0x60819f48 (size=1) Mar 09 09:28:28.298 CPU0: MTS: read access to undefined address 0x3c08002c at pc=0x60819f48 (size=1) Mar 09 09:28:28.548 CPU0: MTS: read access to undefined address 0x3c08002c at pc=0x60819f48 (size=1) Mar 09 09:28:28.563 CPU0: JIT: partial JIT flush (count=186) Mar 09 09:28:28.808 CPU0: MTS: read access to undefined address 0x3c08002c at pc=0x60819f48 (size=1) Mar 09 09:28:28.871 CPU0: JIT: flushing data structures (compiled pages=571) Mar 09 09:28:29.058 CPU0: MTS: read access to undefined address 0x3c08002c at pc=0x60819f48 (size=1) Mar 09 09:28:29.308 CPU0: MTS: read access to undefined address 0x3c08002c at pc=0x60819f48 (size=1) Mar 09 09:28:29.558 CPU0: MTS: read access to undefined address 0x3c08002c at pc=0x60819f48 (size=1) Mar 09 09:28:29.815 CPU0: MTS: read access to undefined address 0x3c08002c at pc=0x60819f48 (size=1) Mar 09 09:28:29.940 CPU0: JIT: partial JIT flush (count=186) Mar 09 09:28:30.034 CPU0: MTS: read access to undefined address 0x3c08002c at pc=0x60819f48 (size=1) Mar 09 09:28:30.284 CPU0: MTS: read access to undefined address 0x3c08002c at pc=0x60819f48 (size=1) Mar 09 09:28:30.542 CPU0: MTS: read access to undefined address 0x3c08002c at pc=0x60819f48 (size=1) Mar 09 09:28:30.799 CPU0: MTS: read access to undefined address 0x3c08002c at pc=0x60819f48 (size=1) Mar 09 09:28:30.955 CPU0: JIT: flushing data structures (compiled pages=566) Mar 09 09:28:31.034 CPU0: MTS: read access to undefined address 0x3c08002c at pc=0x60819f48 (size=1) Mar 09 09:28:31.284 CPU0: MTS: read access to undefined address 0x3c08002c at pc=0x60819f48 (size=1) Mar 09 09:28:31.534 CPU0: MTS: read access to undefined address 0x3c08002c at pc=0x60819f48 (size=1) Mar 09 09:28:31.791 CPU0: MTS: read access to undefined address 0x3c08002c at pc=0x60819f48 (size=1) Mar 09 09:28:32.041 CPU0: MTS: read access to undefined address 0x3c08002c at pc=0x60819f48 (size=1) Mar 09 09:28:32.135 CPU0: JIT: partial JIT flush (count=186) Mar 09 09:28:32.291 CPU0: MTS: read access to undefined address 0x3c08002c at pc=0x60819f48 (size=1) Mar 09 09:28:32.541 CPU0: MTS: read access to undefined address 0x3c08002c at pc=0x60819f48 (size=1) Mar 09 09:28:32.792 CPU0: MTS: read access to undefined address 0x3c08002c at pc=0x60819f48 (size=1) Mar 09 09:28:33.042 CPU0: MTS: read access to undefined address 0x3c08002c at pc=0x60819f48 (size=1) Mar 09 09:28:33.167 CPU0: JIT: flushing data structures (compiled pages=566) Mar 09 09:28:33.292 CPU0: MTS: read access to undefined address 0x3c08002c at pc=0x60819f48 (size=1) Mar 09 09:28:33.542 CPU0: MTS: read access to undefined address 0x3c08002c at pc=0x60819f48 (size=1) Mar 09 09:28:33.792 CPU0: MTS: read access to undefined address 0x3c08002c at pc=0x60819f48 (size=1) Mar 09 09:28:34.042 CPU0: MTS: read access to undefined address 0x3c08002c at pc=0x60819f48 (size=1) Mar 09 09:28:34.198 CPU0: JIT: partial JIT flush (count=183) Mar 09 09:28:34.323 CPU0: MTS: read access to undefined address 0x3c08002c at pc=0x60819f48 (size=1) Mar 09 09:28:34.557 CPU0: MTS: read access to undefined address 0x3c08002c at pc=0x60819f48 (size=1) Mar 09 09:28:34.784 CPU0: MTS: read access to undefined address 0x3c08002c at pc=0x60819f48 (size=1) Mar 09 09:28:34.878 CPU0: JIT: flushing data structures (compiled pages=563) Mar 09 09:28:35.034 CPU0: MTS: read access to undefined address 0x3c08002c at pc=0x60819f48 (size=1) Mar 09 09:28:35.284 CPU0: MTS: read access to undefined address 0x3c08002c at pc=0x60819f48 (size=1) Mar 09 09:28:35.534 CPU0: MTS: read access to undefined address 0x3c08002c at pc=0x60819f48 (size=1) Mar 09 09:28:35.792 CPU0: MTS: read access to undefined address 0x3c08002c at pc=0x60819f48 (size=1) Mar 09 09:28:36.042 CPU0: MTS: read access to undefined address 0x3c08002c at pc=0x60819f48 (size=1) Mar 09 09:28:36.292 CPU0: MTS: read access to undefined address 0x3c08002c at pc=0x60819f48 (size=1) Mar 09 09:28:36.542 CPU0: MTS: read access to undefined address 0x3c08002c at pc=0x60819f48 (size=1) Mar 09 09:28:36.799 CPU0: MTS: read access to undefined address 0x3c08002c at pc=0x60819f48 (size=1) Mar 09 09:28:37.049 CPU0: MTS: read access to undefined address 0x3c08002c at pc=0x60819f48 (size=1) Mar 09 09:28:37.299 CPU0: MTS: read access to undefined address 0x3c08002c at pc=0x60819f48 (size=1) Mar 09 09:28:37.549 CPU0: MTS: read access to undefined address 0x3c08002c at pc=0x60819f48 (size=1) Mar 09 09:28:37.806 CPU0: MTS: read access to undefined address 0x3c08002c at pc=0x60819f48 (size=1) Mar 09 09:28:38.056 CPU0: MTS: read access to undefined address 0x3c08002c at pc=0x60819f48 (size=1) Mar 09 09:28:38.306 CPU0: MTS: read access to undefined address 0x3c08002c at pc=0x60819f48 (size=1) Mar 09 09:28:38.556 CPU0: MTS: read access to undefined address 0x3c08002c at pc=0x60819f48 (size=1) Mar 09 09:28:38.719 CPU0: JIT: partial JIT flush (count=182) Mar 09 09:28:38.813 CPU0: MTS: read access to undefined address 0x3c08002c at pc=0x60819f48 (size=1) Mar 09 09:28:39.032 CPU0: MTS: read access to undefined address 0x3c08002c at pc=0x60819f48 (size=1) Mar 09 09:28:39.282 CPU0: MTS: read access to undefined address 0x3c08002c at pc=0x60819f48 (size=1) Mar 09 09:28:39.532 CPU0: MTS: read access to undefined address 0x3c08002c at pc=0x60819f48 (size=1) Mar 09 09:28:39.794 CPU0: MTS: read access to undefined address 0x3c08002c at pc=0x60819f48 (size=1) Mar 09 09:28:40.052 CPU0: MTS: read access to undefined address 0x3c08002c at pc=0x60819f48 (size=1) Mar 09 09:28:40.146 CPU0: JIT: flushing data structures (compiled pages=570) Mar 09 09:28:40.302 CPU0: MTS: read access to undefined address 0x3c08002c at pc=0x60819f48 (size=1) Mar 09 09:28:40.552 CPU0: MTS: read access to undefined address 0x3c08002c at pc=0x60819f48 (size=1) Mar 09 09:28:40.802 CPU0: MTS: read access to undefined address 0x3c08002c at pc=0x60819f48 (size=1) Mar 09 09:28:40.959 CPU0: JIT: partial JIT flush (count=188) Mar 09 09:28:41.037 CPU0: MTS: read access to undefined address 0x3c08002c at pc=0x60819f48 (size=1) Mar 09 09:28:41.300 CPU0: MTS: read access to undefined address 0x3c08002c at pc=0x60819f48 (size=1) Mar 09 09:28:41.550 CPU0: MTS: read access to undefined address 0x3c08002c at pc=0x60819f48 (size=1) Mar 09 09:28:41.807 CPU0: MTS: read access to undefined address 0x3c08002c at pc=0x60819f48 (size=1) Mar 09 09:28:42.057 CPU0: MTS: read access to undefined address 0x3c08002c at pc=0x60819f48 (size=1) Mar 09 09:28:42.057 C3745_STOP: stopping simulation. Mar 09 09:28:42.057 CPU0: CPU_STATE: Halting CPU (old state=0)... Mar 09 09:28:42.166 DEVICE: Removal of device WIC-1T(0), fd=-1, host_addr=0x0, flags=0 Mar 09 09:28:42.166 VM: shutdown procedure engaged. Mar 09 09:28:42.166 VM_OBJECT: Shutdown of object "slot1" Mar 09 09:28:42.166 DEVICE: Removal of device slot1, fd=-1, host_addr=0x0, flags=2 Mar 09 09:28:42.166 VM_OBJECT: Shutdown of object "slot0" Mar 09 09:28:42.166 DEVICE: Removal of device slot0, fd=-1, host_addr=0x0, flags=2 Mar 09 09:28:42.166 VM_OBJECT: Shutdown of object "ns16552" Mar 09 09:28:42.166 DEVICE: Removal of device ns16552, fd=-1, host_addr=0x0, flags=0 Mar 09 09:28:42.166 VM_OBJECT: Shutdown of object "mem_bswap" Mar 09 09:28:42.166 DEVICE: Removal of device mem_bswap, fd=-1, host_addr=0x0, flags=0 Mar 09 09:28:42.166 VM_OBJECT: Shutdown of object "rom" Mar 09 09:28:42.166 DEVICE: Removal of device rom, fd=14, host_addr=0xed800000, flags=1 Mar 09 09:28:42.166 MMAP: unmapping of device 'rom', fd=14, host_addr=0xed800000, len=0x200000 Mar 09 09:28:42.166 VM_OBJECT: Shutdown of object "ram" Mar 09 09:28:42.166 DEVICE: Removal of device ram, fd=13, host_addr=0xeda00000, flags=34 Mar 09 09:28:42.166 MMAP: unmapping of device 'ram', fd=13, host_addr=0xeda00000, len=0x10000000 Mar 09 09:28:42.260 VM_OBJECT: Shutdown of object "gt96100" Mar 09 09:28:42.260 DEVICE: Removal of device gt96100, fd=-1, host_addr=0x0, flags=0 Mar 09 09:28:42.260 VM_OBJECT: Shutdown of object "io_fpga" Mar 09 09:28:42.260 DEVICE: Removal of device io_fpga, fd=-1, host_addr=0x0, flags=0 Mar 09 09:28:42.260 VM_OBJECT: Shutdown of object "ssa" Mar 09 09:28:42.260 DEVICE: Removal of device ssa, fd=12, host_addr=0xfda00000, flags=2 Mar 09 09:28:42.260 MMAP: unmapping of device 'ssa', fd=12, host_addr=0xfda00000, len=0x7000 Mar 09 09:28:42.260 VM_OBJECT: Shutdown of object "remote_ctrl" Mar 09 09:28:42.260 DEVICE: Removal of device remote_ctrl, fd=-1, host_addr=0x0, flags=0 Mar 09 09:28:42.260 VM: removing PCI busses. Mar 09 09:28:42.260 VM: deleting VTTY. Mar 09 09:28:42.260 VTTY: Console port: closing FD 11 Mar 09 09:28:42.260 VM: deleting system CPUs. Mar 09 09:28:42.260 CPU0: CPU_STATE: Halting CPU (old state=1)... Mar 09 09:28:42.276 VM: shutdown procedure completed. Mar 09 09:28:42.322 VM: trying to shutdown an inactive VM.